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konradybcioandersson
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clk: qcom: mmcc-msm8998: Properly consume GPLL0 inputs
Up until now, the GPLL0_DIV MMSS input has been modeled as a fixed child of MMSS_GPLL0_DIV that's always-on. Properly representing the former in the GCC driver makes us unable to keep doing so. Consume MSS_GPLL0_DIV through fw_name ("gpll0_div") as well as add a fixed .name link to keep backwards compatibility. Reviewed-by: Jeffrey Hugo <[email protected]> Tested-by: Jeffrey Hugo <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
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drivers/clk/qcom/mmcc-msm8998.c

Lines changed: 8 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -46,19 +46,6 @@ enum {
4646
P_DPLINK,
4747
};
4848

49-
static struct clk_fixed_factor gpll0_div = {
50-
.mult = 1,
51-
.div = 2,
52-
.hw.init = &(struct clk_init_data){
53-
.name = "mmss_gpll0_div",
54-
.parent_data = &(const struct clk_parent_data){
55-
.fw_name = "gpll0"
56-
},
57-
.num_parents = 1,
58-
.ops = &clk_fixed_factor_ops,
59-
},
60-
};
61-
6249
static const struct clk_div_table post_div_table_fabia_even[] = {
6350
{ 0x0, 1 },
6451
{ 0x1, 2 },
@@ -354,7 +341,7 @@ static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
354341
static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {
355342
{ .fw_name = "xo" },
356343
{ .fw_name = "gpll0" },
357-
{ .hw = &gpll0_div.hw },
344+
{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
358345
};
359346

360347
static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
@@ -368,7 +355,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
368355
{ .fw_name = "xo" },
369356
{ .hw = &mmpll0_out_even.clkr.hw },
370357
{ .fw_name = "gpll0" },
371-
{ .hw = &gpll0_div.hw },
358+
{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
372359
};
373360

374361
static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
@@ -384,7 +371,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
384371
{ .hw = &mmpll0_out_even.clkr.hw },
385372
{ .hw = &mmpll1_out_even.clkr.hw },
386373
{ .fw_name = "gpll0" },
387-
{ .hw = &gpll0_div.hw },
374+
{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
388375
};
389376

390377
static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
@@ -400,7 +387,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
400387
{ .hw = &mmpll0_out_even.clkr.hw },
401388
{ .hw = &mmpll5_out_even.clkr.hw },
402389
{ .fw_name = "gpll0" },
403-
{ .hw = &gpll0_div.hw },
390+
{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
404391
};
405392

406393
static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[] = {
@@ -418,7 +405,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div
418405
{ .hw = &mmpll3_out_even.clkr.hw },
419406
{ .hw = &mmpll6_out_even.clkr.hw },
420407
{ .fw_name = "gpll0" },
421-
{ .hw = &gpll0_div.hw },
408+
{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
422409
};
423410

424411
static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
@@ -436,7 +423,7 @@ static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_di
436423
{ .hw = &mmpll7_out_even.clkr.hw },
437424
{ .hw = &mmpll10_out_even.clkr.hw },
438425
{ .fw_name = "gpll0" },
439-
{ .hw = &gpll0_div.hw },
426+
{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
440427
};
441428

442429
static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
@@ -454,7 +441,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_di
454441
{ .hw = &mmpll7_out_even.clkr.hw },
455442
{ .hw = &mmpll10_out_even.clkr.hw },
456443
{ .fw_name = "gpll0" },
457-
{ .hw = &gpll0_div.hw },
444+
{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
458445
};
459446

460447
static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
@@ -474,7 +461,7 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_g
474461
{ .hw = &mmpll7_out_even.clkr.hw },
475462
{ .hw = &mmpll10_out_even.clkr.hw },
476463
{ .fw_name = "gpll0" },
477-
{ .hw = &gpll0_div.hw },
464+
{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
478465
};
479466

480467
static struct clk_rcg2 byte0_clk_src = {
@@ -2544,10 +2531,6 @@ static struct clk_branch vmem_ahb_clk = {
25442531
},
25452532
};
25462533

2547-
static struct clk_hw *mmcc_msm8998_hws[] = {
2548-
&gpll0_div.hw,
2549-
};
2550-
25512534
static struct gdsc video_top_gdsc = {
25522535
.gdscr = 0x1024,
25532536
.pd = {
@@ -2855,8 +2838,6 @@ static const struct qcom_cc_desc mmcc_msm8998_desc = {
28552838
.num_resets = ARRAY_SIZE(mmcc_msm8998_resets),
28562839
.gdscs = mmcc_msm8998_gdscs,
28572840
.num_gdscs = ARRAY_SIZE(mmcc_msm8998_gdscs),
2858-
.clk_hws = mmcc_msm8998_hws,
2859-
.num_clk_hws = ARRAY_SIZE(mmcc_msm8998_hws),
28602841
};
28612842

28622843
static const struct of_device_id mmcc_msm8998_match_table[] = {

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