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airliedairlied
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Merge tag 'amd-drm-fixes-6.11-2024-08-14' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.11-2024-08-14: amdgpu: - Fix MES ring buffer overflow - DCN 3.5 fix - DCN 3.2.1 fix - DP MST fix - Cursor fixes - JPEG fixes - Context ops validation - MES 12 fixes - VCN 5.0 fix - HDP fix Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 7c626ce + 23acd1f commit 9370e43

26 files changed

+420
-252
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1057,6 +1057,9 @@ static int amdgpu_cs_patch_ibs(struct amdgpu_cs_parser *p,
10571057
r = amdgpu_ring_parse_cs(ring, p, job, ib);
10581058
if (r)
10591059
return r;
1060+
1061+
if (ib->sa_bo)
1062+
ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
10601063
} else {
10611064
ib->ptr = (uint32_t *)kptr;
10621065
r = amdgpu_ring_patch_cs_in_place(ring, p, job, ib);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -685,16 +685,24 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
685685

686686
switch (args->in.op) {
687687
case AMDGPU_CTX_OP_ALLOC_CTX:
688+
if (args->in.flags)
689+
return -EINVAL;
688690
r = amdgpu_ctx_alloc(adev, fpriv, filp, priority, &id);
689691
args->out.alloc.ctx_id = id;
690692
break;
691693
case AMDGPU_CTX_OP_FREE_CTX:
694+
if (args->in.flags)
695+
return -EINVAL;
692696
r = amdgpu_ctx_free(fpriv, id);
693697
break;
694698
case AMDGPU_CTX_OP_QUERY_STATE:
699+
if (args->in.flags)
700+
return -EINVAL;
695701
r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
696702
break;
697703
case AMDGPU_CTX_OP_QUERY_STATE2:
704+
if (args->in.flags)
705+
return -EINVAL;
698706
r = amdgpu_ctx_query2(adev, fpriv, id, &args->out);
699707
break;
700708
case AMDGPU_CTX_OP_GET_STABLE_PSTATE:

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

Lines changed: 24 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -509,6 +509,16 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id)
509509
int i, r = 0;
510510
int j;
511511

512+
if (adev->enable_mes) {
513+
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
514+
j = i + xcc_id * adev->gfx.num_compute_rings;
515+
amdgpu_mes_unmap_legacy_queue(adev,
516+
&adev->gfx.compute_ring[j],
517+
RESET_QUEUES, 0, 0);
518+
}
519+
return 0;
520+
}
521+
512522
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
513523
return -EINVAL;
514524

@@ -551,6 +561,18 @@ int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id)
551561
int i, r = 0;
552562
int j;
553563

564+
if (adev->enable_mes) {
565+
if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {
566+
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
567+
j = i + xcc_id * adev->gfx.num_gfx_rings;
568+
amdgpu_mes_unmap_legacy_queue(adev,
569+
&adev->gfx.gfx_ring[j],
570+
PREEMPT_QUEUES, 0, 0);
571+
}
572+
}
573+
return 0;
574+
}
575+
554576
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
555577
return -EINVAL;
556578

@@ -995,7 +1017,7 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_
9951017
if (amdgpu_device_skip_hw_access(adev))
9961018
return 0;
9971019

998-
if (adev->mes.ring.sched.ready)
1020+
if (adev->mes.ring[0].sched.ready)
9991021
return amdgpu_mes_rreg(adev, reg);
10001022

10011023
BUG_ON(!ring->funcs->emit_rreg);
@@ -1065,7 +1087,7 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint3
10651087
if (amdgpu_device_skip_hw_access(adev))
10661088
return;
10671089

1068-
if (adev->mes.ring.sched.ready) {
1090+
if (adev->mes.ring[0].sched.ready) {
10691091
amdgpu_mes_wreg(adev, reg, v);
10701092
return;
10711093
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -589,7 +589,8 @@ int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev)
589589
ring = adev->rings[i];
590590
vmhub = ring->vm_hub;
591591

592-
if (ring == &adev->mes.ring ||
592+
if (ring == &adev->mes.ring[0] ||
593+
ring == &adev->mes.ring[1] ||
593594
ring == &adev->umsch_mm.ring)
594595
continue;
595596

@@ -761,7 +762,7 @@ void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev,
761762
unsigned long flags;
762763
uint32_t seq;
763764

764-
if (adev->mes.ring.sched.ready) {
765+
if (adev->mes.ring[0].sched.ready) {
765766
amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1,
766767
ref, mask);
767768
return;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

Lines changed: 51 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -135,9 +135,11 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
135135
idr_init(&adev->mes.queue_id_idr);
136136
ida_init(&adev->mes.doorbell_ida);
137137
spin_lock_init(&adev->mes.queue_id_lock);
138-
spin_lock_init(&adev->mes.ring_lock);
139138
mutex_init(&adev->mes.mutex_hidden);
140139

140+
for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++)
141+
spin_lock_init(&adev->mes.ring_lock[i]);
142+
141143
adev->mes.total_max_queue = AMDGPU_FENCE_MES_QUEUE_ID_MASK;
142144
adev->mes.vmid_mask_mmhub = 0xffffff00;
143145
adev->mes.vmid_mask_gfxhub = 0xffffff00;
@@ -163,36 +165,38 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
163165
adev->mes.sdma_hqd_mask[i] = 0xfc;
164166
}
165167

166-
r = amdgpu_device_wb_get(adev, &adev->mes.sch_ctx_offs);
167-
if (r) {
168-
dev_err(adev->dev,
169-
"(%d) ring trail_fence_offs wb alloc failed\n", r);
170-
goto error_ids;
171-
}
172-
adev->mes.sch_ctx_gpu_addr =
173-
adev->wb.gpu_addr + (adev->mes.sch_ctx_offs * 4);
174-
adev->mes.sch_ctx_ptr =
175-
(uint64_t *)&adev->wb.wb[adev->mes.sch_ctx_offs];
168+
for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) {
169+
r = amdgpu_device_wb_get(adev, &adev->mes.sch_ctx_offs[i]);
170+
if (r) {
171+
dev_err(adev->dev,
172+
"(%d) ring trail_fence_offs wb alloc failed\n",
173+
r);
174+
goto error;
175+
}
176+
adev->mes.sch_ctx_gpu_addr[i] =
177+
adev->wb.gpu_addr + (adev->mes.sch_ctx_offs[i] * 4);
178+
adev->mes.sch_ctx_ptr[i] =
179+
(uint64_t *)&adev->wb.wb[adev->mes.sch_ctx_offs[i]];
176180

177-
r = amdgpu_device_wb_get(adev, &adev->mes.query_status_fence_offs);
178-
if (r) {
179-
amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
180-
dev_err(adev->dev,
181-
"(%d) query_status_fence_offs wb alloc failed\n", r);
182-
goto error_ids;
181+
r = amdgpu_device_wb_get(adev,
182+
&adev->mes.query_status_fence_offs[i]);
183+
if (r) {
184+
dev_err(adev->dev,
185+
"(%d) query_status_fence_offs wb alloc failed\n",
186+
r);
187+
goto error;
188+
}
189+
adev->mes.query_status_fence_gpu_addr[i] = adev->wb.gpu_addr +
190+
(adev->mes.query_status_fence_offs[i] * 4);
191+
adev->mes.query_status_fence_ptr[i] =
192+
(uint64_t *)&adev->wb.wb[adev->mes.query_status_fence_offs[i]];
183193
}
184-
adev->mes.query_status_fence_gpu_addr =
185-
adev->wb.gpu_addr + (adev->mes.query_status_fence_offs * 4);
186-
adev->mes.query_status_fence_ptr =
187-
(uint64_t *)&adev->wb.wb[adev->mes.query_status_fence_offs];
188194

189195
r = amdgpu_device_wb_get(adev, &adev->mes.read_val_offs);
190196
if (r) {
191-
amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
192-
amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
193197
dev_err(adev->dev,
194198
"(%d) read_val_offs alloc failed\n", r);
195-
goto error_ids;
199+
goto error;
196200
}
197201
adev->mes.read_val_gpu_addr =
198202
adev->wb.gpu_addr + (adev->mes.read_val_offs * 4);
@@ -212,10 +216,16 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
212216
error_doorbell:
213217
amdgpu_mes_doorbell_free(adev);
214218
error:
215-
amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
216-
amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
217-
amdgpu_device_wb_free(adev, adev->mes.read_val_offs);
218-
error_ids:
219+
for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) {
220+
if (adev->mes.sch_ctx_ptr[i])
221+
amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]);
222+
if (adev->mes.query_status_fence_ptr[i])
223+
amdgpu_device_wb_free(adev,
224+
adev->mes.query_status_fence_offs[i]);
225+
}
226+
if (adev->mes.read_val_ptr)
227+
amdgpu_device_wb_free(adev, adev->mes.read_val_offs);
228+
219229
idr_destroy(&adev->mes.pasid_idr);
220230
idr_destroy(&adev->mes.gang_id_idr);
221231
idr_destroy(&adev->mes.queue_id_idr);
@@ -226,13 +236,22 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
226236

227237
void amdgpu_mes_fini(struct amdgpu_device *adev)
228238
{
239+
int i;
240+
229241
amdgpu_bo_free_kernel(&adev->mes.event_log_gpu_obj,
230242
&adev->mes.event_log_gpu_addr,
231243
&adev->mes.event_log_cpu_addr);
232244

233-
amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
234-
amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
235-
amdgpu_device_wb_free(adev, adev->mes.read_val_offs);
245+
for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) {
246+
if (adev->mes.sch_ctx_ptr[i])
247+
amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]);
248+
if (adev->mes.query_status_fence_ptr[i])
249+
amdgpu_device_wb_free(adev,
250+
adev->mes.query_status_fence_offs[i]);
251+
}
252+
if (adev->mes.read_val_ptr)
253+
amdgpu_device_wb_free(adev, adev->mes.read_val_offs);
254+
236255
amdgpu_mes_doorbell_free(adev);
237256

238257
idr_destroy(&adev->mes.pasid_idr);
@@ -1499,7 +1518,7 @@ int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe)
14991518

15001519
amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix,
15011520
sizeof(ucode_prefix));
1502-
if (adev->enable_uni_mes && pipe == AMDGPU_MES_SCHED_PIPE) {
1521+
if (adev->enable_uni_mes) {
15031522
snprintf(fw_name, sizeof(fw_name),
15041523
"amdgpu/%s_uni_mes.bin", ucode_prefix);
15051524
} else if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) &&

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -82,8 +82,8 @@ struct amdgpu_mes {
8282
uint64_t default_process_quantum;
8383
uint64_t default_gang_quantum;
8484

85-
struct amdgpu_ring ring;
86-
spinlock_t ring_lock;
85+
struct amdgpu_ring ring[AMDGPU_MAX_MES_PIPES];
86+
spinlock_t ring_lock[AMDGPU_MAX_MES_PIPES];
8787

8888
const struct firmware *fw[AMDGPU_MAX_MES_PIPES];
8989

@@ -112,12 +112,12 @@ struct amdgpu_mes {
112112
uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
113113
uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
114114
uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];
115-
uint32_t sch_ctx_offs;
116-
uint64_t sch_ctx_gpu_addr;
117-
uint64_t *sch_ctx_ptr;
118-
uint32_t query_status_fence_offs;
119-
uint64_t query_status_fence_gpu_addr;
120-
uint64_t *query_status_fence_ptr;
115+
uint32_t sch_ctx_offs[AMDGPU_MAX_MES_PIPES];
116+
uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES];
117+
uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_PIPES];
118+
uint32_t query_status_fence_offs[AMDGPU_MAX_MES_PIPES];
119+
uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_PIPES];
120+
uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_PIPES];
121121
uint32_t read_val_offs;
122122
uint64_t read_val_gpu_addr;
123123
uint32_t *read_val_ptr;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -212,6 +212,8 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
212212
*/
213213
if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
214214
sched_hw_submission = max(sched_hw_submission, 256);
215+
if (ring->funcs->type == AMDGPU_RING_TYPE_MES)
216+
sched_hw_submission = 8;
215217
else if (ring == &adev->sdma.instance[0].page)
216218
sched_hw_submission = 256;
217219

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -461,8 +461,11 @@ struct amdgpu_vcn5_fw_shared {
461461
struct amdgpu_fw_shared_unified_queue_struct sq;
462462
uint8_t pad1[8];
463463
struct amdgpu_fw_shared_fw_logging fw_log;
464+
uint8_t pad2[20];
464465
struct amdgpu_fw_shared_rb_setup rb_setup;
465-
uint8_t pad2[4];
466+
struct amdgpu_fw_shared_smu_interface_info smu_dpm_interface;
467+
struct amdgpu_fw_shared_drm_key_wa drm_key_wa;
468+
uint8_t pad3[9];
466469
};
467470

468471
#define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80

‎drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -858,7 +858,7 @@ void amdgpu_virt_post_reset(struct amdgpu_device *adev)
858858
adev->gfx.is_poweron = false;
859859
}
860860

861-
adev->mes.ring.sched.ready = false;
861+
adev->mes.ring[0].sched.ready = false;
862862
}
863863

864864
bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id)

‎drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

Lines changed: 1 addition & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -3546,42 +3546,17 @@ static int gfx_v12_0_hw_init(void *handle)
35463546
return r;
35473547
}
35483548

3549-
static int gfx_v12_0_kiq_disable_kgq(struct amdgpu_device *adev)
3550-
{
3551-
struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
3552-
struct amdgpu_ring *kiq_ring = &kiq->ring;
3553-
int i, r = 0;
3554-
3555-
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
3556-
return -EINVAL;
3557-
3558-
if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
3559-
adev->gfx.num_gfx_rings))
3560-
return -ENOMEM;
3561-
3562-
for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3563-
kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
3564-
PREEMPT_QUEUES, 0, 0);
3565-
3566-
if (adev->gfx.kiq[0].ring.sched.ready)
3567-
r = amdgpu_ring_test_helper(kiq_ring);
3568-
3569-
return r;
3570-
}
3571-
35723549
static int gfx_v12_0_hw_fini(void *handle)
35733550
{
35743551
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3575-
int r;
35763552
uint32_t tmp;
35773553

35783554
amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
35793555
amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
35803556

35813557
if (!adev->no_hw_access) {
35823558
if (amdgpu_async_gfx_ring) {
3583-
r = gfx_v12_0_kiq_disable_kgq(adev);
3584-
if (r)
3559+
if (amdgpu_gfx_disable_kgq(adev, 0))
35853560
DRM_ERROR("KGQ disable failed\n");
35863561
}
35873562

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