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Merge tag 'qcom-clk-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Pull Qualcomm clk driver updates from Bjorn Andersson: - New drivers to support global, display, gpu, tcsr, and rpmh clocks on Qualcomm SM8650 - Global and RPMh clock support for the Qualcomm X1E80100 SoC - Support for the Stromer APCS PLL found in Qualcomm IPQ5018 - Add a new type of branch clock, with support for controlling separate memory control bits, to the Qualcomm clk driver - Use new branch type in Qualcomm ECPRI clk driver for QDU1000 and QRU1000 - Add a number of missing clocks related to CSI2 on Qualcomm MSM8939 - Add support for the camera clock controller on Qualcomm SC8280XP - Correct PLL configuration in GPU and video clock controllers for Qualcomm SM8150 - Add runtime PM support and a few missing resets to Qualcomm SM8150 video clock controller - Fix configuration of various GCC GDSCs on Qualcomm SM8550 - Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver - Fix up GPU and display clock controllers PLL configuration settings on Qualcomm SM8550 * tag 'qcom-clk-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (41 commits) clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config clk: qcom: dispcc-sm8550: Use the correct PLL configuration function clk: qcom: dispcc-sm8550: Update disp PLL settings clk: qcom: gpucc-sm8550: Update GPU PLL settings clk: qcom: gcc-sm8550: Mark RCGs shared where applicable clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCs clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votable clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flag clk: qcom: camcc-sc8280xp: Prevent error pointer dereference clk: qcom: videocc-sm8150: Add runtime PM support clk: qcom: videocc-sm8150: Add missing PLL config property clk: qcom: videocc-sm8150: Update the videocc resets dt-bindings: clock: Update the videocc resets for sm8150 clk: qcom: rpmh: Add support for X1E80100 rpmh clocks clk: qcom: Add Global Clock controller (GCC) driver for X1E80100 dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for X1E80100 dt-bindings: clock: qcom: Add X1E80100 GCC clocks clk: qcom: Add ECPRICC driver support for QDU1000 and QRU1000 clk: qcom: branch: Add mem ops support for branch2 clocks ...
2 parents b85ea95 + 757d1ca commit 93beaa9

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‎Documentation/devicetree/bindings/clock/qcom,a53pll.yaml

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properties:
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compatible:
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enum:
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- qcom,ipq5018-a53pll
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- qcom,ipq5332-a53pll
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- qcom,ipq6018-a53pll
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- qcom,ipq8074-a53pll

‎Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml

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See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h
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allOf:
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- $ref: qcom,gcc.yaml#
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properties:
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compatible:
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const: qcom,sm8250-camcc
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- const: bi_tcxo_ao
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- const: sleep_clk
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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power-domains:
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items:
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- description: MMCX power domain
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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unevaluatedProperties: false
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examples:
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‎Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq6018.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller on IPQ6018
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maintainers:
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- Stephen Boyd <[email protected]>
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- Taniya Das <[email protected]>
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- Robert Marko <[email protected]>
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description: |
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Qualcomm global clock control module provides the clocks, resets and power
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domains on IPQ6018.
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See also::
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include/dt-bindings/clock/qcom,gcc-ipq6018.h
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include/dt-bindings/reset/qcom,gcc-ipq6018.h
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allOf:
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- $ref: qcom,gcc.yaml#
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properties:
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compatible:
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const: qcom,gcc-ipq6018
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clocks:
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items:
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- description: board XO clock
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- description: sleep clock
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clock-names:
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items:
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- const: xo
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- const: sleep_clk
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required:
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- compatible
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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clock-controller@1800000 {
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compatible = "qcom,gcc-ipq6018";
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reg = <0x01800000 0x80000>;
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clocks = <&xo>, <&sleep_clk>;
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clock-names = "xo", "sleep_clk";
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml

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domains.
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See also::
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include/dt-bindings/clock/qcom,gcc-ipq6018.h
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include/dt-bindings/reset/qcom,gcc-ipq6018.h
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include/dt-bindings/clock/qcom,gcc-msm8953.h
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include/dt-bindings/clock/qcom,gcc-mdm9607.h
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properties:
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compatible:
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enum:
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- qcom,gcc-ipq6018
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- qcom,gcc-mdm9607
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required:

‎Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,qdu1000-ecpricc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm ECPRI Clock & Reset Controller for QDU1000 and QRU1000
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maintainers:
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- Taniya Das <[email protected]>
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- Imran Shaik <[email protected]>
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description: |
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Qualcomm ECPRI Specification V2.0 Common Public Radio Interface clock control
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module which supports the clocks, resets on QDU1000 and QRU1000
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See also:: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
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properties:
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compatible:
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enum:
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- qcom,qdu1000-ecpricc
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 source from GCC
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- description: GPLL1 source from GCC
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- description: GPLL2 source from GCC
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- description: GPLL3 source from GCC
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- description: GPLL4 source from GCC
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- description: GPLL5 source from GCC
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,qdu1000-gcc.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@280000 {
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compatible = "qcom,qdu1000-ecpricc";
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reg = <0x00280000 0x31c00>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>,
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<&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>,
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<&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>,
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<&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>,
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<&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>,
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<&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};

‎Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml

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- qcom,sm8350-rpmh-clk
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- qcom,sm8450-rpmh-clk
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- qcom,sm8550-rpmh-clk
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- qcom,sm8650-rpmh-clk
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- qcom,x1e80100-rpmh-clk
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clocks:
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maxItems: 1

‎Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml

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allOf:
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- $ref: qcom,gcc.yaml#
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- const: iface
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- const: xo
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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maxItems: 1
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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unevaluatedProperties: false
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‎Documentation/devicetree/bindings/clock/qcom,sc7280-camcc.yaml

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allOf:
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- $ref: qcom,gcc.yaml#
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properties:
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compatible:
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- const: bi_tcxo_ao
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- const: sleep_clk
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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maxItems: 1
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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unevaluatedProperties: false
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‎Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml

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allOf:
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- $ref: qcom,gcc.yaml#
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properties:
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compatible:
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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maxItems: 1
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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unevaluatedProperties: false
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‎Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml

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include/dt-bindings/clock/qcom,sm8450-camcc.h
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include/dt-bindings/clock/qcom,sm8550-camcc.h
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include/dt-bindings/clock/qcom,sc8280xp-camcc.h
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allOf:
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- $ref: qcom,gcc.yaml#
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- qcom,sc8280xp-camcc
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- qcom,sm8450-camcc
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- qcom,sm8550-camcc
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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- compatible
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- reg
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- clocks
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- power-domains
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- required-opps
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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unevaluatedProperties: false
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