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bijudasUwe Kleine-König
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Uwe Kleine-König
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dt-bindings: pwm: Add RZ/G2L GPT binding
Add device tree bindings for the General PWM Timer (GPT). Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Biju Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Uwe Kleine-König <[email protected]>
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‎Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pwm/renesas,rzg2l-gpt.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/G2L General PWM Timer (GPT)
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maintainers:
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- Biju Das <[email protected]>
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description: |
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RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-bit timer
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(GPT32E). It supports the following functions
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* 32 bits x 8 channels.
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* Up-counting or down-counting (saw waves) or up/down-counting
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(triangle waves) for each counter.
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* Clock sources independently selectable for each channel.
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* Two I/O pins per channel.
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* Two output compare/input capture registers per channel.
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* For the two output compare/input capture registers of each channel,
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four registers are provided as buffer registers and are capable of
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operating as comparison registers when buffering is not in use.
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* In output compare operation, buffer switching can be at crests or
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troughs, enabling the generation of laterally asymmetric PWM waveforms.
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* Registers for setting up frame cycles in each channel (with capability
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for generating interrupts at overflow or underflow)
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* Generation of dead times in PWM operation.
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* Synchronous starting, stopping and clearing counters for arbitrary
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channels.
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* Starting, stopping, clearing and up/down counters in response to input
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level comparison.
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* Starting, clearing, stopping and up/down counters in response to a
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maximum of four external triggers.
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* Output pin disable function by dead time error and detected
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short-circuits between output pins.
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* A/D converter start triggers can be generated (GPT32E0 to GPT32E3)
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* Enables the noise filter for input capture and external trigger
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operation.
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The below pwm channels are supported.
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pwm0 - GPT32E0.GTIOC0A channel
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pwm1 - GPT32E0.GTIOC0B channel
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pwm2 - GPT32E1.GTIOC1A channel
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pwm3 - GPT32E1.GTIOC1B channel
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pwm4 - GPT32E2.GTIOC2A channel
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pwm5 - GPT32E2.GTIOC2B channel
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pwm6 - GPT32E3.GTIOC3A channel
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pwm7 - GPT32E3.GTIOC3B channel
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pwm8 - GPT32E4.GTIOC4A channel
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pwm9 - GPT32E4.GTIOC4B channel
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pwm10 - GPT32E5.GTIOC5A channel
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pwm11 - GPT32E5.GTIOC5B channel
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pwm12 - GPT32E6.GTIOC6A channel
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pwm13 - GPT32E6.GTIOC6B channel
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pwm14 - GPT32E7.GTIOC7A channel
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pwm15 - GPT32E7.GTIOC7B channel
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properties:
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compatible:
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items:
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- enum:
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- renesas,r9a07g044-gpt # RZ/G2{L,LC}
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- renesas,r9a07g054-gpt # RZ/V2L
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- const: renesas,rzg2l-gpt
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reg:
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maxItems: 1
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'#pwm-cells':
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const: 3
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interrupts:
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items:
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- description: GPT32E0.GTCCRA input capture/compare match
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- description: GPT32E0.GTCCRB input capture/compare
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- description: GPT32E0.GTCCRC compare match
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- description: GPT32E0.GTCCRD compare match
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- description: GPT32E0.GTCCRE compare match
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- description: GPT32E0.GTCCRF compare match
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- description: GPT32E0.GTADTRA compare match
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- description: GPT32E0.GTADTRB compare match
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- description: GPT32E0.GTCNT overflow/GTPR compare match
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- description: GPT32E0.GTCNT underflow
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- description: GPT32E1.GTCCRA input capture/compare match
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- description: GPT32E1.GTCCRB input capture/compare
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- description: GPT32E1.GTCCRC compare match
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- description: GPT32E1.GTCCRD compare match
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- description: GPT32E1.GTCCRE compare match
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- description: GPT32E1.GTCCRF compare match
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- description: GPT32E1.GTADTRA compare match
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- description: GPT32E1.GTADTRB compare match
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- description: GPT32E1.GTCNT overflow/GTPR compare match
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- description: GPT32E1.GTCNT underflow
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- description: GPT32E2.GTCCRA input capture/compare match
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- description: GPT32E2.GTCCRB input capture/compare
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- description: GPT32E2.GTCCRC compare match
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- description: GPT32E2.GTCCRD compare match
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- description: GPT32E2.GTCCRE compare match
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- description: GPT32E2.GTCCRF compare match
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- description: GPT32E2.GTADTRA compare match
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- description: GPT32E2.GTADTRB compare match
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- description: GPT32E2.GTCNT overflow/GTPR compare match
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- description: GPT32E2.GTCNT underflow
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- description: GPT32E3.GTCCRA input capture/compare match
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- description: GPT32E3.GTCCRB input capture/compare
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- description: GPT32E3.GTCCRC compare match
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- description: GPT32E3.GTCCRD compare match
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- description: GPT32E3.GTCCRE compare match
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- description: GPT32E3.GTCCRF compare match
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- description: GPT32E3.GTADTRA compare match
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- description: GPT32E3.GTADTRB compare match
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- description: GPT32E3.GTCNT overflow/GTPR compare match
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- description: GPT32E3.GTCNT underflow
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- description: GPT32E4.GTCCRA input capture/compare match
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- description: GPT32E4.GTCCRB input capture/compare
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- description: GPT32E4.GTCCRC compare match
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- description: GPT32E4.GTCCRD compare match
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- description: GPT32E4.GTCCRE compare match
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- description: GPT32E4.GTCCRF compare match
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- description: GPT32E4.GTADTRA compare match
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- description: GPT32E4.GTADTRB compare match
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- description: GPT32E4.GTCNT overflow/GTPR compare match
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- description: GPT32E4.GTCNT underflow
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- description: GPT32E5.GTCCRA input capture/compare match
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- description: GPT32E5.GTCCRB input capture/compare
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- description: GPT32E5.GTCCRC compare match
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- description: GPT32E5.GTCCRD compare match
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- description: GPT32E5.GTCCRE compare match
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- description: GPT32E5.GTCCRF compare match
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- description: GPT32E5.GTADTRA compare match
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- description: GPT32E5.GTADTRB compare match
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- description: GPT32E5.GTCNT overflow/GTPR compare match
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- description: GPT32E5.GTCNT underflow
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- description: GPT32E6.GTCCRA input capture/compare match
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- description: GPT32E6.GTCCRB input capture/compare
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- description: GPT32E6.GTCCRC compare match
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- description: GPT32E6.GTCCRD compare match
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- description: GPT32E6.GTCCRE compare match
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- description: GPT32E6.GTCCRF compare match
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- description: GPT32E6.GTADTRA compare match
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- description: GPT32E6.GTADTRB compare match
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- description: GPT32E6.GTCNT overflow/GTPR compare match
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- description: GPT32E6.GTCNT underflow
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- description: GPT32E7.GTCCRA input capture/compare match
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- description: GPT32E7.GTCCRB input capture/compare
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- description: GPT32E7.GTCCRC compare match
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- description: GPT32E7.GTCCRD compare match
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- description: GPT32E7.GTCCRE compare match
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- description: GPT32E7.GTCCRF compare match
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- description: GPT32E7.GTADTRA compare match
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- description: GPT32E7.GTADTRB compare match
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- description: GPT32E7.GTCNT overflow/GTPR compare match
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- description: GPT32E7.GTCNT underflow
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interrupt-names:
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items:
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- const: ccmpa0
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- const: ccmpb0
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- const: cmpc0
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- const: cmpd0
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- const: cmpe0
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- const: cmpf0
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- const: adtrga0
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- const: adtrgb0
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- const: ovf0
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- const: unf0
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- const: ccmpa1
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- const: ccmpb1
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- const: cmpc1
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- const: cmpd1
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- const: cmpe1
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- const: cmpf1
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- const: adtrga1
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- const: adtrgb1
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- const: ovf1
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- const: unf1
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- const: ccmpa2
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- const: ccmpb2
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- const: cmpc2
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- const: cmpd2
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- const: cmpe2
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- const: cmpf2
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- const: adtrga2
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- const: adtrgb2
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- const: ovf2
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- const: unf2
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- const: ccmpa3
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- const: ccmpb3
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- const: cmpc3
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- const: cmpd3
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- const: cmpe3
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- const: cmpf3
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- const: adtrga3
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- const: adtrgb3
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- const: ovf3
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- const: unf3
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- const: ccmpa4
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- const: ccmpb4
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- const: cmpc4
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- const: cmpd4
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- const: cmpe4
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- const: cmpf4
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- const: adtrga4
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- const: adtrgb4
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- const: ovf4
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- const: unf4
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- const: ccmpa5
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- const: ccmpb5
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- const: cmpc5
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- const: cmpd5
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- const: cmpe5
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- const: cmpf5
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- const: adtrga5
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- const: adtrgb5
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- const: ovf5
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- const: unf5
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- const: ccmpa6
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- const: ccmpb6
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- const: cmpc6
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- const: cmpd6
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- const: cmpe6
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- const: cmpf6
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- const: adtrga6
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- const: adtrgb6
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- const: ovf6
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- const: unf6
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- const: ccmpa7
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- const: ccmpb7
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- const: cmpc7
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- const: cmpd7
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- const: cmpe7
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- const: cmpf7
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- const: adtrga7
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- const: adtrgb7
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- const: ovf7
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- const: unf7
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clocks:
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maxItems: 1
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- clocks
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- power-domains
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- resets
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allOf:
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- $ref: pwm.yaml#
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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gpt: pwm@10048000 {
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compatible = "renesas,r9a07g044-gpt", "renesas,rzg2l-gpt";
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reg = <0x10048000 0x800>;
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interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 220 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 221 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 222 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 225 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 226 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 227 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 238 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 257 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 258 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 259 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 260 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 261 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 262 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 272 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 273 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 274 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 275 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 278 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 279 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 283 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 284 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 285 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 286 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 287 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 300 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 303 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 304 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 305 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 312 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 313 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 317 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "ccmpa0", "ccmpb0", "cmpc0", "cmpd0",
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"cmpe0", "cmpf0", "adtrga0", "adtrgb0",
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"ovf0", "unf0",
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"ccmpa1", "ccmpb1", "cmpc1", "cmpd1",
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"cmpe1", "cmpf1", "adtrga1", "adtrgb1",
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"ovf1", "unf1",
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"ccmpa2", "ccmpb2", "cmpc2", "cmpd2",
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"cmpe2", "cmpf2", "adtrga2", "adtrgb2",
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"ovf2", "unf2",
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"ccmpa3", "ccmpb3", "cmpc3", "cmpd3",
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"cmpe3", "cmpf3", "adtrga3", "adtrgb3",
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"ovf3", "unf3",
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"ccmpa4", "ccmpb4", "cmpc4", "cmpd4",
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"cmpe4", "cmpf4", "adtrga4", "adtrgb4",
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"ovf4", "unf4",
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"ccmpa5", "ccmpb5", "cmpc5", "cmpd5",
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"cmpe5", "cmpf5", "adtrga5", "adtrgb5",
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"ovf5", "unf5",
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"ccmpa6", "ccmpb6", "cmpc6", "cmpd6",
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"cmpe6", "cmpf6", "adtrga6", "adtrgb6",
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"ovf6", "unf6",
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"ccmpa7", "ccmpb7", "cmpc7", "cmpd7",
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"cmpe7", "cmpf7", "adtrga7", "adtrgb7",
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"ovf7", "unf7";
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clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
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power-domains = <&cpg>;
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resets = <&cpg R9A07G044_GPT_RST_C>;
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#pwm-cells = <3>;
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};

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