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Merge tag 'kvm-riscv-6.7-1' of https://github.com/kvm-riscv/linux into HEAD
KVM/riscv changes for 6.7 - Smstateen and Zicond support for Guest/VM - Virtualized senvcfg CSR for Guest/VM - Added Smstateen registers to the get-reg-list selftests - Added Zicond to the get-reg-list selftests - Virtualized SBI debug console (DBCN) for Guest/VM - Added SBI debug console (DBCN) to the get-reg-list selftests
2 parents ef12ea6 + d9c00f4 commit 957eedc

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14 files changed

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‎Documentation/devicetree/bindings/riscv/extensions.yaml

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -128,6 +128,12 @@ properties:
128128
changes to interrupts as frozen at commit ccbddab ("Merge pull
129129
request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
130130
131+
- const: smstateen
132+
description: |
133+
The standard Smstateen extension for controlling access to CSRs
134+
added by other RISC-V extensions in H/S/VS/U/VU modes and as
135+
ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
136+
131137
- const: ssaia
132138
description: |
133139
The standard Ssaia supervisor-level extension for the advanced
@@ -212,6 +218,12 @@ properties:
212218
ratified in the 20191213 version of the unprivileged ISA
213219
specification.
214220

221+
- const: zicond
222+
description:
223+
The standard Zicond extension for conditional arithmetic and
224+
conditional-select/move operations as ratified in commit 95cf1f9
225+
("Add changes requested by Ved during signoff") of riscv-zicond.
226+
215227
- const: zicsr
216228
description: |
217229
The standard Zicsr extension for control and status register

‎MAINTAINERS

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11570,6 +11570,7 @@ F: arch/riscv/include/asm/kvm*
1157011570
F: arch/riscv/include/uapi/asm/kvm*
1157111571
F: arch/riscv/kvm/
1157211572
F: tools/testing/selftests/kvm/*/riscv/
11573+
F: tools/testing/selftests/kvm/riscv/
1157311574

1157411575
KERNEL VIRTUAL MACHINE for s390 (KVM/s390)
1157511576
M: Christian Borntraeger <[email protected]>

‎arch/riscv/include/asm/csr.h

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -203,6 +203,18 @@
203203
#define ENVCFG_CBIE_INV _AC(0x3, UL)
204204
#define ENVCFG_FIOM _AC(0x1, UL)
205205

206+
/* Smstateen bits */
207+
#define SMSTATEEN0_AIA_IMSIC_SHIFT 58
208+
#define SMSTATEEN0_AIA_IMSIC (_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT)
209+
#define SMSTATEEN0_AIA_SHIFT 59
210+
#define SMSTATEEN0_AIA (_ULL(1) << SMSTATEEN0_AIA_SHIFT)
211+
#define SMSTATEEN0_AIA_ISEL_SHIFT 60
212+
#define SMSTATEEN0_AIA_ISEL (_ULL(1) << SMSTATEEN0_AIA_ISEL_SHIFT)
213+
#define SMSTATEEN0_HSENVCFG_SHIFT 62
214+
#define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
215+
#define SMSTATEEN0_SSTATEEN0_SHIFT 63
216+
#define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
217+
206218
/* symbolic CSR names: */
207219
#define CSR_CYCLE 0xc00
208220
#define CSR_TIME 0xc01
@@ -275,6 +287,8 @@
275287
#define CSR_SIE 0x104
276288
#define CSR_STVEC 0x105
277289
#define CSR_SCOUNTEREN 0x106
290+
#define CSR_SENVCFG 0x10a
291+
#define CSR_SSTATEEN0 0x10c
278292
#define CSR_SSCRATCH 0x140
279293
#define CSR_SEPC 0x141
280294
#define CSR_SCAUSE 0x142
@@ -349,6 +363,10 @@
349363
#define CSR_VSIEH 0x214
350364
#define CSR_VSIPH 0x254
351365

366+
/* Hypervisor stateen CSRs */
367+
#define CSR_HSTATEEN0 0x60c
368+
#define CSR_HSTATEEN0H 0x61c
369+
352370
#define CSR_MSTATUS 0x300
353371
#define CSR_MISA 0x301
354372
#define CSR_MIDELEG 0x303

‎arch/riscv/include/asm/hwcap.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,8 @@
5858
#define RISCV_ISA_EXT_ZICSR 40
5959
#define RISCV_ISA_EXT_ZIFENCEI 41
6060
#define RISCV_ISA_EXT_ZIHPM 42
61+
#define RISCV_ISA_EXT_SMSTATEEN 43
62+
#define RISCV_ISA_EXT_ZICOND 44
6163

6264
#define RISCV_ISA_EXT_MAX 64
6365

‎arch/riscv/include/asm/kvm_host.h

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -162,6 +162,16 @@ struct kvm_vcpu_csr {
162162
unsigned long hvip;
163163
unsigned long vsatp;
164164
unsigned long scounteren;
165+
unsigned long senvcfg;
166+
};
167+
168+
struct kvm_vcpu_config {
169+
u64 henvcfg;
170+
u64 hstateen0;
171+
};
172+
173+
struct kvm_vcpu_smstateen_csr {
174+
unsigned long sstateen0;
165175
};
166176

167177
struct kvm_vcpu_arch {
@@ -183,6 +193,8 @@ struct kvm_vcpu_arch {
183193
unsigned long host_sscratch;
184194
unsigned long host_stvec;
185195
unsigned long host_scounteren;
196+
unsigned long host_senvcfg;
197+
unsigned long host_sstateen0;
186198

187199
/* CPU context of Host */
188200
struct kvm_cpu_context host_context;
@@ -193,6 +205,9 @@ struct kvm_vcpu_arch {
193205
/* CPU CSR context of Guest VCPU */
194206
struct kvm_vcpu_csr guest_csr;
195207

208+
/* CPU Smstateen CSR context of Guest VCPU */
209+
struct kvm_vcpu_smstateen_csr smstateen_csr;
210+
196211
/* CPU context upon Guest VCPU reset */
197212
struct kvm_cpu_context guest_reset_context;
198213

@@ -244,6 +259,9 @@ struct kvm_vcpu_arch {
244259

245260
/* Performance monitoring context */
246261
struct kvm_pmu pmu_context;
262+
263+
/* 'static' configurations which are set only once */
264+
struct kvm_vcpu_config cfg;
247265
};
248266

249267
static inline void kvm_arch_sync_events(struct kvm *kvm) {}

‎arch/riscv/include/asm/kvm_vcpu_sbi.h

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111

1212
#define KVM_SBI_IMPID 3
1313

14-
#define KVM_SBI_VERSION_MAJOR 1
14+
#define KVM_SBI_VERSION_MAJOR 2
1515
#define KVM_SBI_VERSION_MINOR 0
1616

1717
enum kvm_riscv_sbi_ext_status {
@@ -35,6 +35,9 @@ struct kvm_vcpu_sbi_return {
3535
struct kvm_vcpu_sbi_extension {
3636
unsigned long extid_start;
3737
unsigned long extid_end;
38+
39+
bool default_unavail;
40+
3841
/**
3942
* SBI extension handler. It can be defined for a given extension or group of
4043
* extension. But it should always return linux error codes rather than SBI
@@ -59,6 +62,7 @@ int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu,
5962
const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(
6063
struct kvm_vcpu *vcpu, unsigned long extid);
6164
int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run);
65+
void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu);
6266

6367
#ifdef CONFIG_RISCV_SBI_V01
6468
extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01;
@@ -69,6 +73,7 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_ipi;
6973
extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence;
7074
extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_srst;
7175
extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_hsm;
76+
extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_dbcn;
7277
extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental;
7378
extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor;
7479

‎arch/riscv/include/asm/sbi.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ enum sbi_ext_id {
3030
SBI_EXT_HSM = 0x48534D,
3131
SBI_EXT_SRST = 0x53525354,
3232
SBI_EXT_PMU = 0x504D55,
33+
SBI_EXT_DBCN = 0x4442434E,
3334

3435
/* Experimentals extensions must lie within this range */
3536
SBI_EXT_EXPERIMENTAL_START = 0x08000000,
@@ -236,6 +237,12 @@ enum sbi_pmu_ctr_type {
236237
/* Flags defined for counter stop function */
237238
#define SBI_PMU_STOP_FLAG_RESET (1 << 0)
238239

240+
enum sbi_ext_dbcn_fid {
241+
SBI_EXT_DBCN_CONSOLE_WRITE = 0,
242+
SBI_EXT_DBCN_CONSOLE_READ = 1,
243+
SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2,
244+
};
245+
239246
#define SBI_SPEC_VERSION_DEFAULT 0x1
240247
#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
241248
#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f

‎arch/riscv/include/uapi/asm/kvm.h

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,7 @@ struct kvm_riscv_csr {
8080
unsigned long sip;
8181
unsigned long satp;
8282
unsigned long scounteren;
83+
unsigned long senvcfg;
8384
};
8485

8586
/* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
@@ -93,6 +94,11 @@ struct kvm_riscv_aia_csr {
9394
unsigned long iprio2h;
9495
};
9596

97+
/* Smstateen CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
98+
struct kvm_riscv_smstateen_csr {
99+
unsigned long sstateen0;
100+
};
101+
96102
/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
97103
struct kvm_riscv_timer {
98104
__u64 frequency;
@@ -131,6 +137,8 @@ enum KVM_RISCV_ISA_EXT_ID {
131137
KVM_RISCV_ISA_EXT_ZICSR,
132138
KVM_RISCV_ISA_EXT_ZIFENCEI,
133139
KVM_RISCV_ISA_EXT_ZIHPM,
140+
KVM_RISCV_ISA_EXT_SMSTATEEN,
141+
KVM_RISCV_ISA_EXT_ZICOND,
134142
KVM_RISCV_ISA_EXT_MAX,
135143
};
136144

@@ -148,6 +156,7 @@ enum KVM_RISCV_SBI_EXT_ID {
148156
KVM_RISCV_SBI_EXT_PMU,
149157
KVM_RISCV_SBI_EXT_EXPERIMENTAL,
150158
KVM_RISCV_SBI_EXT_VENDOR,
159+
KVM_RISCV_SBI_EXT_DBCN,
151160
KVM_RISCV_SBI_EXT_MAX,
152161
};
153162

@@ -178,10 +187,13 @@ enum KVM_RISCV_SBI_EXT_ID {
178187
#define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
179188
#define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
180189
#define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
190+
#define KVM_REG_RISCV_CSR_SMSTATEEN (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
181191
#define KVM_REG_RISCV_CSR_REG(name) \
182192
(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
183193
#define KVM_REG_RISCV_CSR_AIA_REG(name) \
184194
(offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long))
195+
#define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name) \
196+
(offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long))
185197

186198
/* Timer registers are mapped as type 4 */
187199
#define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT)

‎arch/riscv/kernel/cpufeature.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -167,6 +167,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
167167
__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
168168
__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
169169
__RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
170+
__RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
170171
__RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
171172
__RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
172173
__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
@@ -175,6 +176,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
175176
__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
176177
__RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
177178
__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
179+
__RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
178180
__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
179181
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
180182
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),

‎arch/riscv/kvm/vcpu.c

Lines changed: 63 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -141,6 +141,12 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
141141
if (rc)
142142
return rc;
143143

144+
/*
145+
* Setup SBI extensions
146+
* NOTE: This must be the last thing to be initialized.
147+
*/
148+
kvm_riscv_vcpu_sbi_init(vcpu);
149+
144150
/* Reset VCPU */
145151
kvm_riscv_reset_vcpu(vcpu);
146152

@@ -471,31 +477,38 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
471477
return -EINVAL;
472478
}
473479

474-
static void kvm_riscv_vcpu_update_config(const unsigned long *isa)
480+
static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu)
475481
{
476-
u64 henvcfg = 0;
482+
const unsigned long *isa = vcpu->arch.isa;
483+
struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
477484

478485
if (riscv_isa_extension_available(isa, SVPBMT))
479-
henvcfg |= ENVCFG_PBMTE;
486+
cfg->henvcfg |= ENVCFG_PBMTE;
480487

481488
if (riscv_isa_extension_available(isa, SSTC))
482-
henvcfg |= ENVCFG_STCE;
489+
cfg->henvcfg |= ENVCFG_STCE;
483490

484491
if (riscv_isa_extension_available(isa, ZICBOM))
485-
henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE);
492+
cfg->henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE);
486493

487494
if (riscv_isa_extension_available(isa, ZICBOZ))
488-
henvcfg |= ENVCFG_CBZE;
489-
490-
csr_write(CSR_HENVCFG, henvcfg);
491-
#ifdef CONFIG_32BIT
492-
csr_write(CSR_HENVCFGH, henvcfg >> 32);
493-
#endif
495+
cfg->henvcfg |= ENVCFG_CBZE;
496+
497+
if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
498+
cfg->hstateen0 |= SMSTATEEN0_HSENVCFG;
499+
if (riscv_isa_extension_available(isa, SSAIA))
500+
cfg->hstateen0 |= SMSTATEEN0_AIA_IMSIC |
501+
SMSTATEEN0_AIA |
502+
SMSTATEEN0_AIA_ISEL;
503+
if (riscv_isa_extension_available(isa, SMSTATEEN))
504+
cfg->hstateen0 |= SMSTATEEN0_SSTATEEN0;
505+
}
494506
}
495507

496508
void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
497509
{
498510
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
511+
struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
499512

500513
csr_write(CSR_VSSTATUS, csr->vsstatus);
501514
csr_write(CSR_VSIE, csr->vsie);
@@ -506,8 +519,14 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
506519
csr_write(CSR_VSTVAL, csr->vstval);
507520
csr_write(CSR_HVIP, csr->hvip);
508521
csr_write(CSR_VSATP, csr->vsatp);
509-
510-
kvm_riscv_vcpu_update_config(vcpu->arch.isa);
522+
csr_write(CSR_HENVCFG, cfg->henvcfg);
523+
if (IS_ENABLED(CONFIG_32BIT))
524+
csr_write(CSR_HENVCFGH, cfg->henvcfg >> 32);
525+
if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
526+
csr_write(CSR_HSTATEEN0, cfg->hstateen0);
527+
if (IS_ENABLED(CONFIG_32BIT))
528+
csr_write(CSR_HSTATEEN0H, cfg->hstateen0 >> 32);
529+
}
511530

512531
kvm_riscv_gstage_update_hgatp(vcpu);
513532

@@ -606,6 +625,32 @@ static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu)
606625
kvm_riscv_vcpu_aia_update_hvip(vcpu);
607626
}
608627

628+
static __always_inline void kvm_riscv_vcpu_swap_in_guest_state(struct kvm_vcpu *vcpu)
629+
{
630+
struct kvm_vcpu_smstateen_csr *smcsr = &vcpu->arch.smstateen_csr;
631+
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
632+
struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
633+
634+
vcpu->arch.host_senvcfg = csr_swap(CSR_SENVCFG, csr->senvcfg);
635+
if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) &&
636+
(cfg->hstateen0 & SMSTATEEN0_SSTATEEN0))
637+
vcpu->arch.host_sstateen0 = csr_swap(CSR_SSTATEEN0,
638+
smcsr->sstateen0);
639+
}
640+
641+
static __always_inline void kvm_riscv_vcpu_swap_in_host_state(struct kvm_vcpu *vcpu)
642+
{
643+
struct kvm_vcpu_smstateen_csr *smcsr = &vcpu->arch.smstateen_csr;
644+
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
645+
struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
646+
647+
csr->senvcfg = csr_swap(CSR_SENVCFG, vcpu->arch.host_senvcfg);
648+
if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) &&
649+
(cfg->hstateen0 & SMSTATEEN0_SSTATEEN0))
650+
smcsr->sstateen0 = csr_swap(CSR_SSTATEEN0,
651+
vcpu->arch.host_sstateen0);
652+
}
653+
609654
/*
610655
* Actually run the vCPU, entering an RCU extended quiescent state (EQS) while
611656
* the vCPU is running.
@@ -615,10 +660,12 @@ static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu)
615660
*/
616661
static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu)
617662
{
663+
kvm_riscv_vcpu_swap_in_guest_state(vcpu);
618664
guest_state_enter_irqoff();
619665
__kvm_riscv_switch_to(&vcpu->arch);
620666
vcpu->arch.last_exit_cpu = vcpu->cpu;
621667
guest_state_exit_irqoff();
668+
kvm_riscv_vcpu_swap_in_host_state(vcpu);
622669
}
623670

624671
int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
@@ -627,6 +674,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
627674
struct kvm_cpu_trap trap;
628675
struct kvm_run *run = vcpu->run;
629676

677+
if (!vcpu->arch.ran_atleast_once)
678+
kvm_riscv_vcpu_setup_config(vcpu);
679+
630680
/* Mark this VCPU ran at least once */
631681
vcpu->arch.ran_atleast_once = true;
632682

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