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Merge tag 'drm-xilinx-dpsub-20200718' of git://linuxtv.org/pinchartl/media into drm-next
Xilinx ZynqMP DisplayPort Subsystem driver Signed-off-by: Dave Airlie <[email protected]> From: Laurent Pinchart <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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‎Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx ZynqMP DisplayPort Subsystem
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description: |
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The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
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implements the display and audio pipelines based on the DisplayPort v1.2
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standard. The subsystem includes multiple functional blocks as below:
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+------------------------------------------------------------+
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+--------+ | +----------------+ +-----------+ |
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| DPDMA | --->| | --> | Video | Video +-------------+ |
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| 4x vid | | | | | Rendering | -+--> | | | +------+
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| 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
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+--------+ | | Buffer Manager | +-----------+ | | Source | | +------+
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| | and STC | +-----------+ | | Controller | | +------+
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Live Video --->| | --> | Audio | Audio | |---> | PHY1 |
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| | | | Mixer | --+-> | | | +------+
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Live Audio --->| | --> | | || +-------------+ |
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| +----------------+ +-----------+ || |
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+---------------------------------------||-------------------+
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vv
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Blended Video and
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Mixed Audio to PL
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The Buffer Manager interacts with external interface such as DMA engines or
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live audio/video streams from the programmable logic. The Video Rendering
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Pipeline blends the video and graphics layers and performs colorspace
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conversion. The Audio Mixer mixes the incoming audio streams. The DisplayPort
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Source Controller handles the DisplayPort protocol and connects to external
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PHYs.
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The subsystem supports 2 video and 2 audio streams, and various pixel formats
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and depths up to 4K@30 resolution.
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Please refer to "Zynq UltraScale+ Device Technical Reference Manual"
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(https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)
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for more details.
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maintainers:
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- Laurent Pinchart <[email protected]>
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properties:
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compatible:
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const: xlnx,zynqmp-dpsub-1.7
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reg:
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maxItems: 4
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reg-names:
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items:
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- const: dp
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- const: blend
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- const: av_buf
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- const: aud
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interrupts:
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maxItems: 1
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clocks:
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description:
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The APB clock and at least one video clock are mandatory, the audio clock
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is optional.
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minItems: 2
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maxItems: 4
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items:
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- description: dp_apb_clk is the APB clock
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- description: dp_aud_clk is the Audio clock
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- description:
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dp_vtc_pixel_clk_in is the non-live video clock (from Processing
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System)
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- description:
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dp_live_video_in_clk is the live video clock (from Programmable
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Logic)
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clock-names:
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oneOf:
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- minItems: 2
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maxItems: 3
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items:
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- const: dp_apb_clk
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- enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
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- enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
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- minItems: 3
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maxItems: 4
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items:
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- const: dp_apb_clk
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- const: dp_aud_clk
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- enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
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- enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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dmas:
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maxItems: 4
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items:
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- description: Video layer, plane 0 (RGB or luma)
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- description: Video layer, plane 1 (U/V or U)
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- description: Video layer, plane 2 (V)
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- description: Graphics layer
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dma-names:
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items:
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- const: vid0
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- const: vid1
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- const: vid2
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- const: gfx0
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phys:
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description: PHYs for the DP data lanes
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minItems: 1
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maxItems: 2
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phy-names:
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minItems: 1
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maxItems: 2
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items:
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- const: dp-phy0
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- const: dp-phy1
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- clocks
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- clock-names
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- power-domains
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- resets
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- dmas
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- dma-names
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- phys
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- phy-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
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display@fd4a0000 {
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compatible = "xlnx,zynqmp-dpsub-1.7";
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reg = <0x0 0xfd4a0000 0x0 0x1000>,
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<0x0 0xfd4aa000 0x0 0x1000>,
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<0x0 0xfd4ab000 0x0 0x1000>,
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<0x0 0xfd4ac000 0x0 0x1000>;
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reg-names = "dp", "blend", "av_buf", "aud";
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interrupts = <0 119 4>;
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interrupt-parent = <&gic>;
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clock-names = "dp_apb_clk", "dp_aud_clk", "dp_live_video_in_clk";
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clocks = <&dp_aclk>, <&clkc 17>, <&si570_1>;
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power-domains = <&pd_dp>;
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resets = <&reset ZYNQMP_RESET_DP>;
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dma-names = "vid0", "vid1", "vid2", "gfx0";
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dmas = <&xlnx_dpdma 0>,
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<&xlnx_dpdma 1>,
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<&xlnx_dpdma 2>,
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<&xlnx_dpdma 3>;
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phys = <&psgtr 1 PHY_TYPE_DP 0 3 27000000>,
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<&psgtr 0 PHY_TYPE_DP 1 3 27000000>;
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phy-names = "dp-phy0", "dp-phy1";
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};
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...

‎Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx ZynqMP DisplayPort DMA Controller Device Tree Bindings
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description: |
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These bindings describe the DMA engine included in the Xilinx ZynqMP
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DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3
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channels for a video stream, 1 channel for a graphics stream, and 2 channels
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for an audio stream).
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maintainers:
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- Laurent Pinchart <[email protected]>
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allOf:
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- $ref: "../dma-controller.yaml#"
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properties:
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"#dma-cells":
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const: 1
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description: |
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The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
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for a list of channel IDs).
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compatible:
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const: xlnx,zynqmp-dpdma
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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description: The AXI clock
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maxItems: 1
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clock-names:
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const: axi_clk
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required:
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- "#dma-cells"
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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dma: dma-controller@fd4c0000 {
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compatible = "xlnx,zynqmp-dpdma";
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reg = <0x0 0xfd4c0000 0x0 0x1000>;
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interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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clocks = <&dpdma_clk>;
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clock-names = "axi_clk";
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#dma-cells = <1>;
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};
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...

‎Documentation/driver-api/dmaengine/client.rst

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- interleaved_dma: This is common to Slave as well as M2M clients. For slave
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address of devices' fifo could be already known to the driver.
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Various types of operations could be expressed by setting
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appropriate values to the 'dma_interleaved_template' members.
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appropriate values to the 'dma_interleaved_template' members. Cyclic
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interleaved DMA transfers are also possible if supported by the channel by
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setting the DMA_PREP_REPEAT transfer flag.
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A non-NULL return of this transfer API represents a "descriptor" for
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the given transaction.

‎Documentation/driver-api/dmaengine/provider.rst

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want to transfer a portion of uncompressed data directly to the
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display to print it
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- DMA_REPEAT
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- The device supports repeated transfers. A repeated transfer, indicated by
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the DMA_PREP_REPEAT transfer flag, is similar to a cyclic transfer in that
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it gets automatically repeated when it ends, but can additionally be
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replaced by the client.
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- This feature is limited to interleaved transfers, this flag should thus not
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be set if the DMA_INTERLEAVE flag isn't set. This limitation is based on
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the current needs of DMA clients, support for additional transfer types
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should be added in the future if and when the need arises.
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- DMA_LOAD_EOT
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- The device supports replacing repeated transfers at end of transfer (EOT)
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by queuing a new transfer with the DMA_PREP_LOAD_EOT flag set.
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- Support for replacing a currently running transfer at another point (such
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as end of burst instead of end of transfer) will be added in the future
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based on DMA clients needs, if and when the need arises.
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These various types will also affect how the source and destination
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addresses change over time.
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writes for which the descriptor should be in different format from
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normal data descriptors.
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- DMA_PREP_REPEAT
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- If set, the transfer will be automatically repeated when it ends until a
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new transfer is queued on the same channel with the DMA_PREP_LOAD_EOT flag.
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If the next transfer to be queued on the channel does not have the
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DMA_PREP_LOAD_EOT flag set, the current transfer will be repeated until the
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client terminates all transfers.
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- This flag is only supported if the channel reports the DMA_REPEAT
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capability.
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- DMA_PREP_LOAD_EOT
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- If set, the transfer will replace the transfer currently being executed at
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the end of the transfer.
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- This is the default behaviour for non-repeated transfers, specifying
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DMA_PREP_LOAD_EOT for non-repeated transfers will thus make no difference.
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- When using repeated transfers, DMA clients will usually need to set the
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DMA_PREP_LOAD_EOT flag on all transfers, otherwise the channel will keep
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repeating the last repeated transfer and ignore the new transfers being
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queued. Failure to set DMA_PREP_LOAD_EOT will appear as if the channel was
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stuck on the previous transfer.
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- This flag is only supported if the channel reports the DMA_LOAD_EOT
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capability.
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General Design Notes
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====================
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‎MAINTAINERS

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F: Documentation/gpu/xen-front.rst
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F: drivers/gpu/drm/xen/
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DRM DRIVERS FOR XILINX
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M: Hyun Kwon <[email protected]>
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M: Laurent Pinchart <[email protected]>
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L: [email protected]
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S: Maintained
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T: git git://anongit.freedesktop.org/drm/drm-misc
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F: Documentation/devicetree/bindings/display/xlnx/
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F: drivers/gpu/drm/xlnx/
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DRM DRIVERS FOR ZTE ZX
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M: Shawn Guo <[email protected]>
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L: [email protected]
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F: drivers/media/platform/xilinx/
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F: include/uapi/linux/xilinx-v4l2-controls.h
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XILINX ZYNQMP DPDMA DRIVER
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M: Hyun Kwon <[email protected]>
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M: Laurent Pinchart <[email protected]>
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L: [email protected]
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S: Supported
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F: Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml
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F: drivers/dma/xilinx/xilinx_dpdma.c
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F: include/dt-bindings/dma/xlnx-zynqmp-dpdma.h
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XILLYBUS DRIVER
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M: Eli Billauer <[email protected]>
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L: [email protected]

‎drivers/dma/Kconfig

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help
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Enable support for Xilinx ZynqMP DMA controller.
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config XILINX_ZYNQMP_DPDMA
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tristate "Xilinx DPDMA Engine"
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Enable support for Xilinx ZynqMP DisplayPort DMA. Choose this option
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if you have a Xilinx ZynqMP SoC with a DisplayPort subsystem. The
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driver provides the dmaengine required by the DisplayPort subsystem
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display driver.
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config ZX_DMA
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tristate "ZTE ZX DMA support"
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depends on ARCH_ZX || COMPILE_TEST

‎drivers/dma/xilinx/Makefile

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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o
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obj-$(CONFIG_XILINX_ZYNQMP_DMA) += zynqmp_dma.o
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obj-$(CONFIG_XILINX_ZYNQMP_DPDMA) += xilinx_dpdma.o

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