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42 | 42 | #define TCR_KASAN_FLAGS 0
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43 | 43 | #endif
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44 | 44 |
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45 |
| -#define MAIR(attr, mt) ((attr) << ((mt) * 8)) |
| 45 | +/* Default MAIR_EL1 */ |
| 46 | +#define MAIR_EL1_SET \ |
| 47 | + (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) | \ |
| 48 | + MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) | \ |
| 49 | + MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) | \ |
| 50 | + MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) | \ |
| 51 | + MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) | \ |
| 52 | + MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT)) |
46 | 53 |
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47 | 54 | #ifdef CONFIG_CPU_PM
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48 | 55 | /**
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@@ -416,23 +423,9 @@ ENTRY(__cpu_setup)
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416 | 423 | enable_dbg // since this is per-cpu
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417 | 424 | reset_pmuserenr_el0 x0 // Disable PMU access from EL0
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418 | 425 | /*
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419 |
| - * Memory region attributes for LPAE: |
420 |
| - * |
421 |
| - * n = AttrIndx[2:0] |
422 |
| - * n MAIR |
423 |
| - * DEVICE_nGnRnE 000 00000000 |
424 |
| - * DEVICE_nGnRE 001 00000100 |
425 |
| - * DEVICE_GRE 010 00001100 |
426 |
| - * NORMAL_NC 011 01000100 |
427 |
| - * NORMAL 100 11111111 |
428 |
| - * NORMAL_WT 101 10111011 |
| 426 | + * Memory region attributes |
429 | 427 | */
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430 |
| - ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ |
431 |
| - MAIR(0x04, MT_DEVICE_nGnRE) | \ |
432 |
| - MAIR(0x0c, MT_DEVICE_GRE) | \ |
433 |
| - MAIR(0x44, MT_NORMAL_NC) | \ |
434 |
| - MAIR(0xff, MT_NORMAL) | \ |
435 |
| - MAIR(0xbb, MT_NORMAL_WT) |
| 428 | + mov_q x5, MAIR_EL1_SET |
436 | 429 | msr mair_el1, x5
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437 | 430 | /*
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438 | 431 | * Prepare SCTLR
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