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142 | 142 |
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143 | 143 | #define QSPI_GLOBAL_CONFIG 0X1a4
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144 | 144 | #define QSPI_CMB_SEQ_EN BIT(0)
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| 145 | +#define QSPI_TPM_WAIT_POLL_EN BIT(1) |
145 | 146 |
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146 | 147 | #define QSPI_CMB_SEQ_ADDR 0x1a8
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147 | 148 | #define QSPI_ADDRESS_VALUE_SET(X) (((x) & 0xFFFF) << 0)
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164 | 165 | struct tegra_qspi_soc_data {
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165 | 166 | bool has_dma;
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166 | 167 | bool cmb_xfer_capable;
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| 168 | + bool supports_tpm; |
167 | 169 | unsigned int cs_count;
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168 | 170 | };
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169 | 171 |
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@@ -1065,6 +1067,12 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
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1065 | 1067 |
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1066 | 1068 | /* Enable Combined sequence mode */
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1067 | 1069 | val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
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| 1070 | + if (spi->mode & SPI_TPM_HW_FLOW) { |
| 1071 | + if (tqspi->soc_data->supports_tpm) |
| 1072 | + val |= QSPI_TPM_WAIT_POLL_EN; |
| 1073 | + else |
| 1074 | + return -EIO; |
| 1075 | + } |
1068 | 1076 | val |= QSPI_CMB_SEQ_EN;
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1069 | 1077 | tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
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1070 | 1078 | /* Process individual transfer list */
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@@ -1196,6 +1204,8 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi,
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1196 | 1204 | /* Disable Combined sequence mode */
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1197 | 1205 | val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG);
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1198 | 1206 | val &= ~QSPI_CMB_SEQ_EN;
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| 1207 | + if (tqspi->soc_data->supports_tpm) |
| 1208 | + val &= ~QSPI_TPM_WAIT_POLL_EN; |
1199 | 1209 | tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG);
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1200 | 1210 | list_for_each_entry(transfer, &msg->transfers, transfer_list) {
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1201 | 1211 | struct spi_transfer *xfer = transfer;
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@@ -1454,24 +1464,28 @@ static irqreturn_t tegra_qspi_isr_thread(int irq, void *context_data)
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1454 | 1464 | static struct tegra_qspi_soc_data tegra210_qspi_soc_data = {
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1455 | 1465 | .has_dma = true,
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1456 | 1466 | .cmb_xfer_capable = false,
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| 1467 | + .supports_tpm = false, |
1457 | 1468 | .cs_count = 1,
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1458 | 1469 | };
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1459 | 1470 |
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1460 | 1471 | static struct tegra_qspi_soc_data tegra186_qspi_soc_data = {
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1461 | 1472 | .has_dma = true,
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1462 | 1473 | .cmb_xfer_capable = true,
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| 1474 | + .supports_tpm = false, |
1463 | 1475 | .cs_count = 1,
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1464 | 1476 | };
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1465 | 1477 |
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1466 | 1478 | static struct tegra_qspi_soc_data tegra234_qspi_soc_data = {
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1467 | 1479 | .has_dma = false,
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1468 | 1480 | .cmb_xfer_capable = true,
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| 1481 | + .supports_tpm = true, |
1469 | 1482 | .cs_count = 1,
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1470 | 1483 | };
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1471 | 1484 |
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1472 | 1485 | static struct tegra_qspi_soc_data tegra241_qspi_soc_data = {
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1473 | 1486 | .has_dma = false,
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1474 | 1487 | .cmb_xfer_capable = true,
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| 1488 | + .supports_tpm = true, |
1475 | 1489 | .cs_count = 4,
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1476 | 1490 | };
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1477 | 1491 |
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