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1 parent 78c9480 commit 96c9b51Copy full SHA for 96c9b51
Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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title: i.MX8M DDR Controller
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maintainers:
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- - Leonard Crestez <leonard.crestez@nxp.com>
+ - Peng Fan <peng.fan@nxp.com>
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description:
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The DDRC block is integrated in i.MX8M for interfacing with DDR based
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