@@ -47,6 +47,13 @@ static const struct reg_sequence cs35l56_patch_fw[] = {
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{ CS35L56_MAIN_POSTURE_NUMBER , 0x00000000 },
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};
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+ static const struct reg_sequence cs35l63_patch_fw [] = {
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+ /* These are not reset by a soft-reset, so patch to defaults. */
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+ { CS35L63_MAIN_RENDER_USER_MUTE , 0x00000000 },
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+ { CS35L63_MAIN_RENDER_USER_VOLUME , 0x00000000 },
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+ { CS35L63_MAIN_POSTURE_NUMBER , 0x00000000 },
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+ };
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+
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int cs35l56_set_patch (struct cs35l56_base * cs35l56_base )
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{
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int ret ;
@@ -64,6 +71,10 @@ int cs35l56_set_patch(struct cs35l56_base *cs35l56_base)
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ret = regmap_register_patch (cs35l56_base -> regmap , cs35l56_patch_fw ,
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ARRAY_SIZE (cs35l56_patch_fw ));
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break ;
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+ case 0x63 :
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+ ret = regmap_register_patch (cs35l56_base -> regmap , cs35l63_patch_fw ,
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+ ARRAY_SIZE (cs35l63_patch_fw ));
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+ break ;
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default :
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break ;
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}
@@ -102,6 +113,36 @@ static const struct reg_default cs35l56_reg_defaults[] = {
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{ CS35L56_MAIN_POSTURE_NUMBER , 0x00000000 },
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};
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+ static const struct reg_default cs35l63_reg_defaults [] = {
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+ /* no defaults for OTP_MEM - first read populates cache */
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+
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+ { CS35L56_ASP1_ENABLES1 , 0x00000000 },
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+ { CS35L56_ASP1_CONTROL1 , 0x00000028 },
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+ { CS35L56_ASP1_CONTROL2 , 0x18180200 },
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+ { CS35L56_ASP1_CONTROL3 , 0x00000002 },
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+ { CS35L56_ASP1_FRAME_CONTROL1 , 0x03020100 },
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+ { CS35L56_ASP1_FRAME_CONTROL5 , 0x00020100 },
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+ { CS35L56_ASP1_DATA_CONTROL1 , 0x00000018 },
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+ { CS35L56_ASP1_DATA_CONTROL5 , 0x00000018 },
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+ { CS35L56_ASP1TX1_INPUT , 0x00000000 },
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+ { CS35L56_ASP1TX2_INPUT , 0x00000000 },
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+ { CS35L56_ASP1TX3_INPUT , 0x00000000 },
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+ { CS35L56_ASP1TX4_INPUT , 0x00000000 },
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+ { CS35L56_SWIRE_DP3_CH1_INPUT , 0x00000018 },
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+ { CS35L56_SWIRE_DP3_CH2_INPUT , 0x00000019 },
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+ { CS35L56_SWIRE_DP3_CH3_INPUT , 0x00000029 },
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+ { CS35L56_SWIRE_DP3_CH4_INPUT , 0x00000028 },
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+ { CS35L56_IRQ1_MASK_1 , 0x8003ffff },
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+ { CS35L56_IRQ1_MASK_2 , 0xffff7fff },
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+ { CS35L56_IRQ1_MASK_4 , 0xe0ffffff },
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+ { CS35L56_IRQ1_MASK_8 , 0x8c000fff },
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+ { CS35L56_IRQ1_MASK_18 , 0x0760f000 },
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+ { CS35L56_IRQ1_MASK_20 , 0x15c00000 },
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+ { CS35L63_MAIN_RENDER_USER_MUTE , 0x00000000 },
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+ { CS35L63_MAIN_RENDER_USER_VOLUME , 0x00000000 },
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+ { CS35L63_MAIN_POSTURE_NUMBER , 0x00000000 },
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+ };
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+
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static bool cs35l56_is_dsp_memory (unsigned int reg )
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{
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switch (reg ) {
@@ -199,7 +240,7 @@ static bool cs35l56_precious_reg(struct device *dev, unsigned int reg)
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}
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}
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- static bool cs35l56_volatile_reg ( struct device * dev , unsigned int reg )
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+ static bool cs35l56_common_volatile_reg ( unsigned int reg )
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{
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switch (reg ) {
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case CS35L56_DEVID :
@@ -237,12 +278,32 @@ static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg)
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case CS35L56_DSP1_SCRATCH3 :
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case CS35L56_DSP1_SCRATCH4 :
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return true;
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+ default :
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+ return cs35l56_is_dsp_memory (reg );
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+ }
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+ }
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+
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+ static bool cs35l56_volatile_reg (struct device * dev , unsigned int reg )
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+ {
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+ switch (reg ) {
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case CS35L56_MAIN_RENDER_USER_MUTE :
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case CS35L56_MAIN_RENDER_USER_VOLUME :
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case CS35L56_MAIN_POSTURE_NUMBER :
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return false;
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default :
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- return cs35l56_is_dsp_memory (reg );
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+ return cs35l56_common_volatile_reg (reg );
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+ }
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+ }
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+
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+ static bool cs35l63_volatile_reg (struct device * dev , unsigned int reg )
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+ {
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+ switch (reg ) {
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+ case CS35L63_MAIN_RENDER_USER_MUTE :
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+ case CS35L63_MAIN_RENDER_USER_VOLUME :
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+ case CS35L63_MAIN_POSTURE_NUMBER :
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+ return false;
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+ default :
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+ return cs35l56_common_volatile_reg (reg );
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}
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}
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@@ -405,6 +466,11 @@ static const struct reg_sequence cs35l56_system_reset_seq[] = {
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REG_SEQ0 (CS35L56_DSP_VIRTUAL1_MBOX_1 , CS35L56_MBOX_CMD_SYSTEM_RESET ),
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};
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+ static const struct reg_sequence cs35l63_system_reset_seq [] = {
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+ REG_SEQ0 (CS35L63_DSP1_HALO_STATE , 0 ),
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+ REG_SEQ0 (CS35L56_DSP_VIRTUAL1_MBOX_1 , CS35L56_MBOX_CMD_SYSTEM_RESET ),
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+ };
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+
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void cs35l56_system_reset (struct cs35l56_base * cs35l56_base , bool is_soundwire )
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{
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/*
@@ -426,6 +492,11 @@ void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire)
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cs35l56_system_reset_seq ,
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ARRAY_SIZE (cs35l56_system_reset_seq ));
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break ;
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+ case 0x63 :
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+ regmap_multi_reg_write_bypassed (cs35l56_base -> regmap ,
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+ cs35l63_system_reset_seq ,
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+ ARRAY_SIZE (cs35l63_system_reset_seq ));
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+ break ;
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default :
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break ;
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}
@@ -844,6 +915,9 @@ int cs35l56_hw_init(struct cs35l56_base *cs35l56_base)
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case 0x35A56 :
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case 0x35A57 :
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break ;
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+ case 0x35A630 :
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+ devid = devid >> 4 ;
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+ break ;
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default :
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dev_err (cs35l56_base -> dev , "Unknown device %x\n" , devid );
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return ret ;
@@ -1080,6 +1154,39 @@ const struct regmap_config cs35l56_regmap_sdw = {
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};
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EXPORT_SYMBOL_NS_GPL (cs35l56_regmap_sdw , "SND_SOC_CS35L56_SHARED" );
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+ const struct regmap_config cs35l63_regmap_i2c = {
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+ .reg_bits = 32 ,
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+ .val_bits = 32 ,
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+ .reg_stride = 4 ,
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+ .reg_base = 0x8000 ,
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+ .reg_format_endian = REGMAP_ENDIAN_BIG ,
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+ .val_format_endian = REGMAP_ENDIAN_BIG ,
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+ .max_register = CS35L56_DSP1_PMEM_5114 ,
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+ .reg_defaults = cs35l63_reg_defaults ,
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+ .num_reg_defaults = ARRAY_SIZE (cs35l63_reg_defaults ),
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+ .volatile_reg = cs35l63_volatile_reg ,
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+ .readable_reg = cs35l56_readable_reg ,
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+ .precious_reg = cs35l56_precious_reg ,
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+ .cache_type = REGCACHE_MAPLE ,
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+ };
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+ EXPORT_SYMBOL_NS_GPL (cs35l63_regmap_i2c , "SND_SOC_CS35L56_SHARED" );
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+
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+ const struct regmap_config cs35l63_regmap_sdw = {
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+ .reg_bits = 32 ,
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+ .val_bits = 32 ,
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+ .reg_stride = 4 ,
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+ .reg_format_endian = REGMAP_ENDIAN_LITTLE ,
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+ .val_format_endian = REGMAP_ENDIAN_BIG ,
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+ .max_register = CS35L56_DSP1_PMEM_5114 ,
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+ .reg_defaults = cs35l63_reg_defaults ,
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+ .num_reg_defaults = ARRAY_SIZE (cs35l63_reg_defaults ),
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+ .volatile_reg = cs35l63_volatile_reg ,
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+ .readable_reg = cs35l56_readable_reg ,
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+ .precious_reg = cs35l56_precious_reg ,
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+ .cache_type = REGCACHE_MAPLE ,
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+ };
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+ EXPORT_SYMBOL_NS_GPL (cs35l63_regmap_sdw , "SND_SOC_CS35L56_SHARED" );
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+
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const struct cs35l56_fw_reg cs35l56_fw_reg = {
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.fw_ver = CS35L56_DSP1_FW_VER ,
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.halo_state = CS35L56_DSP1_HALO_STATE ,
@@ -1092,6 +1199,18 @@ const struct cs35l56_fw_reg cs35l56_fw_reg = {
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};
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EXPORT_SYMBOL_NS_GPL (cs35l56_fw_reg , "SND_SOC_CS35L56_SHARED" );
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+ const struct cs35l56_fw_reg cs35l63_fw_reg = {
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+ .fw_ver = CS35L63_DSP1_FW_VER ,
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+ .halo_state = CS35L63_DSP1_HALO_STATE ,
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+ .pm_cur_stat = CS35L63_DSP1_PM_CUR_STATE ,
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+ .prot_sts = CS35L63_PROTECTION_STATUS ,
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+ .transducer_actual_ps = CS35L63_TRANSDUCER_ACTUAL_PS ,
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+ .user_mute = CS35L63_MAIN_RENDER_USER_MUTE ,
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+ .user_volume = CS35L63_MAIN_RENDER_USER_VOLUME ,
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+ .posture_number = CS35L63_MAIN_POSTURE_NUMBER ,
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+ };
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+ EXPORT_SYMBOL_NS_GPL (cs35l63_fw_reg , "SND_SOC_CS35L56_SHARED" );
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+
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MODULE_DESCRIPTION ("ASoC CS35L56 Shared" );
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MODULE_AUTHOR (
"Richard Fitzgerald <[email protected] >" );
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MODULE_AUTHOR (
"Simon Trimmer <[email protected] >" );
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