Skip to content

Commit 9a85eb4

Browse files
Sowjanya Komatinenithierryreding
Sowjanya Komatineni
authored and
thierryreding
committed
clk: tegra: Add support for OSC_DIV fixed clocks
Tegra30 through Tegra210 has OSC_DIV2 and OSC_DIV4 fixed clocks from the OSC pads. This patch adds support for these clocks. Tested-by: Dmitry Osipenko <[email protected]> Reviewed-by: Dmitry Osipenko <[email protected]> Signed-off-by: Sowjanya Komatineni <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
1 parent 5e7322b commit 9a85eb4

File tree

6 files changed

+34
-0
lines changed

6 files changed

+34
-0
lines changed

‎drivers/clk/tegra/clk-id.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,8 @@ enum clk_id {
4646
tegra_clk_clk_m,
4747
tegra_clk_clk_m_div2,
4848
tegra_clk_clk_m_div4,
49+
tegra_clk_osc_div2,
50+
tegra_clk_osc_div4,
4951
tegra_clk_clk_out_1,
5052
tegra_clk_clk_out_1_mux,
5153
tegra_clk_clk_out_2,

‎drivers/clk/tegra/clk-tegra-fixed.c

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,22 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
4848

4949
osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);
5050

51+
/* osc_div2 */
52+
dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div2, clks);
53+
if (dt_clk) {
54+
clk = clk_register_fixed_factor(NULL, "osc_div2", "osc",
55+
0, 1, 2);
56+
*dt_clk = clk;
57+
}
58+
59+
/* osc_div4 */
60+
dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div4, clks);
61+
if (dt_clk) {
62+
clk = clk_register_fixed_factor(NULL, "osc_div4", "osc",
63+
0, 1, 4);
64+
*dt_clk = clk;
65+
}
66+
5167
dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
5268
if (!dt_clk)
5369
return 0;

‎drivers/clk/tegra/clk-tegra114.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -737,6 +737,8 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
737737
[tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
738738
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
739739
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
740+
[tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },
741+
[tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },
740742
[tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
741743
[tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
742744
[tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
@@ -817,6 +819,8 @@ static struct tegra_devclk devclks[] __initdata = {
817819
{ .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
818820
{ .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
819821
{ .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
822+
{ .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },
823+
{ .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },
820824
{ .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
821825
{ .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
822826
{ .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },

‎drivers/clk/tegra/clk-tegra124.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -862,6 +862,8 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
862862
[tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
863863
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
864864
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
865+
[tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },
866+
[tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },
865867
[tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
866868
[tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
867869
[tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
@@ -943,6 +945,8 @@ static struct tegra_devclk devclks[] __initdata = {
943945
{ .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
944946
{ .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
945947
{ .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
948+
{ .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },
949+
{ .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },
946950
{ .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
947951
{ .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
948952
{ .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },

‎drivers/clk/tegra/clk-tegra210.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2373,6 +2373,8 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
23732373
[tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
23742374
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },
23752375
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },
2376+
[tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true },
2377+
[tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true },
23762378
[tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
23772379
[tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true },
23782380
[tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true },
@@ -2499,6 +2501,8 @@ static struct tegra_devclk devclks[] __initdata = {
24992501
{ .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
25002502
{ .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
25012503
{ .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },
2504+
{ .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },
2505+
{ .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },
25022506
{ .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
25032507
{ .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },
25042508
{ .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },

‎drivers/clk/tegra/clk-tegra30.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -583,6 +583,8 @@ static struct tegra_devclk devclks[] __initdata = {
583583
{ .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
584584
{ .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
585585
{ .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
586+
{ .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 },
587+
{ .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 },
586588
{ .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
587589
{ .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
588590
{ .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
@@ -685,6 +687,8 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
685687
[tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
686688
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
687689
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
690+
[tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },
691+
[tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },
688692
[tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
689693
[tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
690694
[tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },

0 commit comments

Comments
 (0)