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bebarinobebarino
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Merge tag 'renesas-clk-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull more Renesas clk driver updates from Geert Uytterhoeven: - Add Ethernet, SDHI, DMA, and HyperFLASH/QSPI (RPC-IF) clocks on R-Car V4M - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a779h0: Add RPC-IF clock clk: renesas: r8a779h0: Add SYS-DMAC clocks clk: renesas: r8a779h0: Add SDHI clock clk: renesas: r8a779h0: Add EtherAVB clocks clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 mux clk: renesas: r8a779f0: Correct PFC/GPIO parent clock clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks
2 parents a24f93f + 81a7a88 commit 9bd5726

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6 files changed

+21
-12
lines changed

6 files changed

+21
-12
lines changed

‎drivers/clk/renesas/r8a779f0-cpg-mssr.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,7 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
161161
DEF_MOD("cmt1", 911, R8A779F0_CLK_R),
162162
DEF_MOD("cmt2", 912, R8A779F0_CLK_R),
163163
DEF_MOD("cmt3", 913, R8A779F0_CLK_R),
164-
DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M),
164+
DEF_MOD("pfc0", 915, R8A779F0_CLK_CPEX),
165165
DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M),
166166
DEF_MOD("rswitch2", 1505, R8A779F0_CLK_RSW2),
167167
DEF_MOD("ether-serdes", 1506, R8A779F0_CLK_S0D2_HSC),

‎drivers/clk/renesas/r8a779g0-cpg-mssr.c

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@
2222

2323
enum clk_ids {
2424
/* Core Clock Outputs exported to DT */
25-
LAST_DT_CORE_CLK = R8A779G0_CLK_R,
25+
LAST_DT_CORE_CLK = R8A779G0_CLK_CP,
2626

2727
/* External Input Clocks */
2828
CLK_EXTAL,
@@ -141,6 +141,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
141141
DEF_FIXED("svd2_vip", R8A779G0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1),
142142
DEF_FIXED("cbfusa", R8A779G0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
143143
DEF_FIXED("cpex", R8A779G0_CLK_CPEX, CLK_EXTAL, 2, 1),
144+
DEF_FIXED("cp", R8A779G0_CLK_CP, CLK_EXTAL, 2, 1),
144145
DEF_FIXED("viobus", R8A779G0_CLK_VIOBUS, CLK_VIO, 1, 1),
145146
DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
146147
DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
@@ -232,10 +233,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
232233
DEF_MOD("cmt1", 911, R8A779G0_CLK_R),
233234
DEF_MOD("cmt2", 912, R8A779G0_CLK_R),
234235
DEF_MOD("cmt3", 913, R8A779G0_CLK_R),
235-
DEF_MOD("pfc0", 915, R8A779G0_CLK_CL16M),
236-
DEF_MOD("pfc1", 916, R8A779G0_CLK_CL16M),
237-
DEF_MOD("pfc2", 917, R8A779G0_CLK_CL16M),
238-
DEF_MOD("pfc3", 918, R8A779G0_CLK_CL16M),
236+
DEF_MOD("pfc0", 915, R8A779G0_CLK_CP),
237+
DEF_MOD("pfc1", 916, R8A779G0_CLK_CP),
238+
DEF_MOD("pfc2", 917, R8A779G0_CLK_CP),
239+
DEF_MOD("pfc3", 918, R8A779G0_CLK_CP),
239240
DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M),
240241
DEF_MOD("tsn", 2723, R8A779G0_CLK_S0D4_HSC),
241242
DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),

‎drivers/clk/renesas/r8a779h0-cpg-mssr.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -173,6 +173,9 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = {
173173
};
174174

175175
static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
176+
DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC),
177+
DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC),
178+
DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC),
176179
DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1),
177180
DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1),
178181
DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1),
@@ -181,6 +184,10 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
181184
DEF_MOD("i2c1", 519, R8A779H0_CLK_S0D6_PER),
182185
DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER),
183186
DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER),
187+
DEF_MOD("rpc-if", 629, R8A779H0_CLK_RPCD2),
188+
DEF_MOD("sdhi0", 706, R8A779H0_CLK_SD0),
189+
DEF_MOD("sydm1", 709, R8A779H0_CLK_S0D6_PER),
190+
DEF_MOD("sydm2", 710, R8A779H0_CLK_S0D6_PER),
184191
DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R),
185192
DEF_MOD("pfc0", 915, R8A779H0_CLK_CP),
186193
DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),

‎drivers/clk/renesas/r9a07g043-cpg.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,7 @@ static const struct clk_div_table dtable_1_32[] = {
8888
/* Mux clock tables */
8989
static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
9090
static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
91-
static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
91+
static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" };
9292

9393
static const u32 mtable_sdhi[] = { 1, 2, 3 };
9494

@@ -137,9 +137,9 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
137137
DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2),
138138
DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
139139
DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
140-
DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi,
140+
DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi,
141141
mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
142-
DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi,
142+
DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_sdhi,
143143
mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
144144
DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4),
145145
DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4),

‎drivers/clk/renesas/r9a07g044-cpg.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,7 @@ static const struct clk_div_table dtable_16_128[] = {
106106
static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
107107
static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" };
108108
static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
109-
static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
109+
static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" };
110110
static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
111111

112112
static const u32 mtable_sdhi[] = { 1, 2, 3 };
@@ -176,9 +176,9 @@ static const struct {
176176
DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2),
177177
DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
178178
DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
179-
DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_shdi,
179+
DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi,
180180
mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
181-
DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, SEL_SDHI0_STS, sel_shdi,
181+
DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_sdhi,
182182
mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
183183
DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
184184
DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),

‎include/dt-bindings/clock/r8a779g0-cpg-mssr.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -86,5 +86,6 @@
8686
#define R8A779G0_CLK_CPEX 74
8787
#define R8A779G0_CLK_CBFUSA 75
8888
#define R8A779G0_CLK_R 76
89+
#define R8A779G0_CLK_CP 77
8990

9091
#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */

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