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bjdooks-ctbebarino
bjdooks-ct
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clk: hisilicon: fix sparse warnings in clk-hi3670.c
Fix the following warnings from sparse by removing the 0 initialiser that is actually a pointer. drivers/clk/hisilicon/clk-hi3670.c:298:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:300:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:302:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:304:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:306:63: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:308:63: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:310:63: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:312:63: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:314:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:316:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:318:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:320:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:322:63: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:324:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:326:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:328:63: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:330:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:332:63: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:334:63: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:336:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:338:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:340:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:342:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:344:63: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:346:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:348:65: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:350:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:352:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:488:69: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:490:70: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:492:70: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:494:69: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:496:70: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:498:69: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:500:69: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:502:70: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:504:69: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:506:69: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:508:69: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:510:70: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:512:69: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:514:70: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:516:69: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:518:70: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:520:69: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:522:69: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:524:70: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:526:70: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:528:69: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:530:69: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:532:70: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:534:71: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:536:71: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:538:69: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:611:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:614:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:616:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:653:70: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:655:70: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:657:70: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:659:70: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:661:70: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:663:70: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:665:70: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:735:63: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:737:63: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:739:63: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:741:63: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:743:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:745:64: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:802:69: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:804:69: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:806:69: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:808:69: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:810:70: warning: Using plain integer as NULL pointer drivers/clk/hisilicon/clk-hi3670.c:812:69: warning: Using plain integer as NULL pointer Signed-off-by: Ben Dooks <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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‎drivers/clk/hisilicon/clk-hi3670.c

Lines changed: 76 additions & 76 deletions
Original file line numberDiff line numberDiff line change
@@ -295,61 +295,61 @@ static const struct hisi_gate_clock hi3670_crgctrl_gate_sep_clks[] = {
295295

296296
static const struct hisi_gate_clock hi3670_crgctrl_gate_clks[] = {
297297
{ HI3670_AUTODIV_SYSBUS, "autodiv_sysbus", "clk_div_sysbus",
298-
CLK_SET_RATE_PARENT, 0x404, 5, CLK_GATE_HIWORD_MASK, 0, },
298+
CLK_SET_RATE_PARENT, 0x404, 5, CLK_GATE_HIWORD_MASK, },
299299
{ HI3670_AUTODIV_EMMC0BUS, "autodiv_emmc0bus", "autodiv_sysbus",
300-
CLK_SET_RATE_PARENT, 0x404, 1, CLK_GATE_HIWORD_MASK, 0, },
300+
CLK_SET_RATE_PARENT, 0x404, 1, CLK_GATE_HIWORD_MASK, },
301301
{ HI3670_PCLK_ANDGT_MMC1_PCIE, "pclk_andgt_mmc1_pcie", "clk_div_320m",
302-
CLK_SET_RATE_PARENT, 0xf8, 13, CLK_GATE_HIWORD_MASK, 0, },
302+
CLK_SET_RATE_PARENT, 0xf8, 13, CLK_GATE_HIWORD_MASK, },
303303
{ HI3670_CLK_GATE_VCODECBUS_GT, "clk_gate_vcodecbus_gt", "clk_mux_vcodecbus",
304-
CLK_SET_RATE_PARENT, 0x0F0, 8, CLK_GATE_HIWORD_MASK, 0, },
304+
CLK_SET_RATE_PARENT, 0x0F0, 8, CLK_GATE_HIWORD_MASK, },
305305
{ HI3670_CLK_ANDGT_SD, "clk_andgt_sd", "clk_mux_sd_pll",
306-
CLK_SET_RATE_PARENT, 0xF4, 3, CLK_GATE_HIWORD_MASK, 0, },
306+
CLK_SET_RATE_PARENT, 0xF4, 3, CLK_GATE_HIWORD_MASK, },
307307
{ HI3670_CLK_SD_SYS_GT, "clk_sd_sys_gt", "clkin_sys",
308-
CLK_SET_RATE_PARENT, 0xF4, 5, CLK_GATE_HIWORD_MASK, 0, },
308+
CLK_SET_RATE_PARENT, 0xF4, 5, CLK_GATE_HIWORD_MASK, },
309309
{ HI3670_CLK_ANDGT_SDIO, "clk_andgt_sdio", "clk_mux_sdio_pll",
310-
CLK_SET_RATE_PARENT, 0xF4, 8, CLK_GATE_HIWORD_MASK, 0, },
310+
CLK_SET_RATE_PARENT, 0xF4, 8, CLK_GATE_HIWORD_MASK, },
311311
{ HI3670_CLK_SDIO_SYS_GT, "clk_sdio_sys_gt", "clkin_sys",
312-
CLK_SET_RATE_PARENT, 0xF4, 6, CLK_GATE_HIWORD_MASK, 0, },
312+
CLK_SET_RATE_PARENT, 0xF4, 6, CLK_GATE_HIWORD_MASK, },
313313
{ HI3670_CLK_A53HPM_ANDGT, "clk_a53hpm_andgt", "clk_mux_a53hpm",
314-
CLK_SET_RATE_PARENT, 0x0F4, 7, CLK_GATE_HIWORD_MASK, 0, },
314+
CLK_SET_RATE_PARENT, 0x0F4, 7, CLK_GATE_HIWORD_MASK, },
315315
{ HI3670_CLK_320M_PLL_GT, "clk_320m_pll_gt", "clk_mux_320m",
316-
CLK_SET_RATE_PARENT, 0xF8, 10, CLK_GATE_HIWORD_MASK, 0, },
316+
CLK_SET_RATE_PARENT, 0xF8, 10, CLK_GATE_HIWORD_MASK, },
317317
{ HI3670_CLK_ANDGT_UARTH, "clk_andgt_uarth", "clk_div_320m",
318-
CLK_SET_RATE_PARENT, 0xF4, 11, CLK_GATE_HIWORD_MASK, 0, },
318+
CLK_SET_RATE_PARENT, 0xF4, 11, CLK_GATE_HIWORD_MASK, },
319319
{ HI3670_CLK_ANDGT_UARTL, "clk_andgt_uartl", "clk_div_320m",
320-
CLK_SET_RATE_PARENT, 0xF4, 10, CLK_GATE_HIWORD_MASK, 0, },
320+
CLK_SET_RATE_PARENT, 0xF4, 10, CLK_GATE_HIWORD_MASK, },
321321
{ HI3670_CLK_ANDGT_UART0, "clk_andgt_uart0", "clk_div_320m",
322-
CLK_SET_RATE_PARENT, 0xF4, 9, CLK_GATE_HIWORD_MASK, 0, },
322+
CLK_SET_RATE_PARENT, 0xF4, 9, CLK_GATE_HIWORD_MASK, },
323323
{ HI3670_CLK_ANDGT_SPI, "clk_andgt_spi", "clk_div_320m",
324-
CLK_SET_RATE_PARENT, 0xF4, 13, CLK_GATE_HIWORD_MASK, 0, },
324+
CLK_SET_RATE_PARENT, 0xF4, 13, CLK_GATE_HIWORD_MASK, },
325325
{ HI3670_CLK_ANDGT_PCIEAXI, "clk_andgt_pcieaxi", "clk_mux_pcieaxi",
326-
CLK_SET_RATE_PARENT, 0xfc, 15, CLK_GATE_HIWORD_MASK, 0, },
326+
CLK_SET_RATE_PARENT, 0xfc, 15, CLK_GATE_HIWORD_MASK, },
327327
{ HI3670_CLK_DIV_AO_ASP_GT, "clk_div_ao_asp_gt", "clk_mux_ao_asp",
328-
CLK_SET_RATE_PARENT, 0xF4, 4, CLK_GATE_HIWORD_MASK, 0, },
328+
CLK_SET_RATE_PARENT, 0xF4, 4, CLK_GATE_HIWORD_MASK, },
329329
{ HI3670_CLK_GATE_CSI_TRANS, "clk_gate_csi_trans", "clk_ppll2",
330-
CLK_SET_RATE_PARENT, 0xF4, 14, CLK_GATE_HIWORD_MASK, 0, },
330+
CLK_SET_RATE_PARENT, 0xF4, 14, CLK_GATE_HIWORD_MASK, },
331331
{ HI3670_CLK_GATE_DSI_TRANS, "clk_gate_dsi_trans", "clk_ppll2",
332-
CLK_SET_RATE_PARENT, 0xF4, 1, CLK_GATE_HIWORD_MASK, 0, },
332+
CLK_SET_RATE_PARENT, 0xF4, 1, CLK_GATE_HIWORD_MASK, },
333333
{ HI3670_CLK_ANDGT_PTP, "clk_andgt_ptp", "clk_div_320m",
334-
CLK_SET_RATE_PARENT, 0xF8, 5, CLK_GATE_HIWORD_MASK, 0, },
334+
CLK_SET_RATE_PARENT, 0xF8, 5, CLK_GATE_HIWORD_MASK, },
335335
{ HI3670_CLK_ANDGT_OUT0, "clk_andgt_out0", "clk_ppll0",
336-
CLK_SET_RATE_PARENT, 0xF0, 10, CLK_GATE_HIWORD_MASK, 0, },
336+
CLK_SET_RATE_PARENT, 0xF0, 10, CLK_GATE_HIWORD_MASK, },
337337
{ HI3670_CLK_ANDGT_OUT1, "clk_andgt_out1", "clk_ppll0",
338-
CLK_SET_RATE_PARENT, 0xF0, 11, CLK_GATE_HIWORD_MASK, 0, },
338+
CLK_SET_RATE_PARENT, 0xF0, 11, CLK_GATE_HIWORD_MASK, },
339339
{ HI3670_CLKGT_DP_AUDIO_PLL_AO, "clkgt_dp_audio_pll_ao", "clk_ppll6",
340-
CLK_SET_RATE_PARENT, 0xF8, 15, CLK_GATE_HIWORD_MASK, 0, },
340+
CLK_SET_RATE_PARENT, 0xF8, 15, CLK_GATE_HIWORD_MASK, },
341341
{ HI3670_CLK_ANDGT_VDEC, "clk_andgt_vdec", "clk_mux_vdec",
342-
CLK_SET_RATE_PARENT, 0xF0, 13, CLK_GATE_HIWORD_MASK, 0, },
342+
CLK_SET_RATE_PARENT, 0xF0, 13, CLK_GATE_HIWORD_MASK, },
343343
{ HI3670_CLK_ANDGT_VENC, "clk_andgt_venc", "clk_mux_venc",
344-
CLK_SET_RATE_PARENT, 0xF0, 9, CLK_GATE_HIWORD_MASK, 0, },
344+
CLK_SET_RATE_PARENT, 0xF0, 9, CLK_GATE_HIWORD_MASK, },
345345
{ HI3670_CLK_ISP_SNCLK_ANGT, "clk_isp_snclk_angt", "clk_div_a53hpm",
346-
CLK_SET_RATE_PARENT, 0x108, 2, CLK_GATE_HIWORD_MASK, 0, },
346+
CLK_SET_RATE_PARENT, 0x108, 2, CLK_GATE_HIWORD_MASK, },
347347
{ HI3670_CLK_ANDGT_RXDPHY, "clk_andgt_rxdphy", "clk_div_a53hpm",
348-
CLK_SET_RATE_PARENT, 0x0F0, 12, CLK_GATE_HIWORD_MASK, 0, },
348+
CLK_SET_RATE_PARENT, 0x0F0, 12, CLK_GATE_HIWORD_MASK, },
349349
{ HI3670_CLK_ANDGT_ICS, "clk_andgt_ics", "clk_mux_ics",
350-
CLK_SET_RATE_PARENT, 0xf0, 14, CLK_GATE_HIWORD_MASK, 0, },
350+
CLK_SET_RATE_PARENT, 0xf0, 14, CLK_GATE_HIWORD_MASK, },
351351
{ HI3670_AUTODIV_DMABUS, "autodiv_dmabus", "autodiv_sysbus",
352-
CLK_SET_RATE_PARENT, 0x404, 3, CLK_GATE_HIWORD_MASK, 0, },
352+
CLK_SET_RATE_PARENT, 0x404, 3, CLK_GATE_HIWORD_MASK, },
353353
};
354354

355355
static const char *const
@@ -485,57 +485,57 @@ static const struct hisi_mux_clock hi3670_crgctrl_mux_clks[] = {
485485

486486
static const struct hisi_divider_clock hi3670_crgctrl_divider_clks[] = {
487487
{ HI3670_CLK_DIV_CFGBUS, "clk_div_cfgbus", "clk_div_sysbus",
488-
CLK_SET_RATE_PARENT, 0xEC, 0, 2, CLK_DIVIDER_HIWORD_MASK, 0, },
488+
CLK_SET_RATE_PARENT, 0xEC, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
489489
{ HI3670_CLK_DIV_MMC0BUS, "clk_div_mmc0bus", "autodiv_emmc0bus",
490-
CLK_SET_RATE_PARENT, 0x0EC, 2, 1, CLK_DIVIDER_HIWORD_MASK, 0, },
490+
CLK_SET_RATE_PARENT, 0x0EC, 2, 1, CLK_DIVIDER_HIWORD_MASK, },
491491
{ HI3670_CLK_DIV_MMC1BUS, "clk_div_mmc1bus", "clk_div_sysbus",
492-
CLK_SET_RATE_PARENT, 0x0EC, 3, 1, CLK_DIVIDER_HIWORD_MASK, 0, },
492+
CLK_SET_RATE_PARENT, 0x0EC, 3, 1, CLK_DIVIDER_HIWORD_MASK, },
493493
{ HI3670_PCLK_DIV_MMC1_PCIE, "pclk_div_mmc1_pcie", "pclk_andgt_mmc1_pcie",
494-
CLK_SET_RATE_PARENT, 0xb4, 6, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
494+
CLK_SET_RATE_PARENT, 0xb4, 6, 4, CLK_DIVIDER_HIWORD_MASK, },
495495
{ HI3670_CLK_DIV_VCODECBUS, "clk_div_vcodecbus", "clk_gate_vcodecbus_gt",
496-
CLK_SET_RATE_PARENT, 0x0BC, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
496+
CLK_SET_RATE_PARENT, 0x0BC, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
497497
{ HI3670_CLK_DIV_SD, "clk_div_sd", "clk_andgt_sd",
498-
CLK_SET_RATE_PARENT, 0xB8, 0, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
498+
CLK_SET_RATE_PARENT, 0xB8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
499499
{ HI3670_CLK_DIV_SDIO, "clk_div_sdio", "clk_andgt_sdio",
500-
CLK_SET_RATE_PARENT, 0xC0, 0, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
500+
CLK_SET_RATE_PARENT, 0xC0, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
501501
{ HI3670_CLK_DIV_UARTH, "clk_div_uarth", "clk_andgt_uarth",
502-
CLK_SET_RATE_PARENT, 0xB0, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
502+
CLK_SET_RATE_PARENT, 0xB0, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
503503
{ HI3670_CLK_DIV_UARTL, "clk_div_uartl", "clk_andgt_uartl",
504-
CLK_SET_RATE_PARENT, 0xB0, 8, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
504+
CLK_SET_RATE_PARENT, 0xB0, 8, 4, CLK_DIVIDER_HIWORD_MASK, },
505505
{ HI3670_CLK_DIV_UART0, "clk_div_uart0", "clk_andgt_uart0",
506-
CLK_SET_RATE_PARENT, 0xB0, 4, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
506+
CLK_SET_RATE_PARENT, 0xB0, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
507507
{ HI3670_CLK_DIV_I2C, "clk_div_i2c", "clk_div_320m",
508-
CLK_SET_RATE_PARENT, 0xE8, 4, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
508+
CLK_SET_RATE_PARENT, 0xE8, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
509509
{ HI3670_CLK_DIV_SPI, "clk_div_spi", "clk_andgt_spi",
510-
CLK_SET_RATE_PARENT, 0xC4, 12, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
510+
CLK_SET_RATE_PARENT, 0xC4, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
511511
{ HI3670_CLK_DIV_PCIEAXI, "clk_div_pcieaxi", "clk_andgt_pcieaxi",
512-
CLK_SET_RATE_PARENT, 0xb4, 0, 5, CLK_DIVIDER_HIWORD_MASK, 0, },
512+
CLK_SET_RATE_PARENT, 0xb4, 0, 5, CLK_DIVIDER_HIWORD_MASK, },
513513
{ HI3670_CLK_DIV_AO_ASP, "clk_div_ao_asp", "clk_div_ao_asp_gt",
514-
CLK_SET_RATE_PARENT, 0x108, 6, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
514+
CLK_SET_RATE_PARENT, 0x108, 6, 4, CLK_DIVIDER_HIWORD_MASK, },
515515
{ HI3670_CLK_DIV_CSI_TRANS, "clk_div_csi_trans", "clk_gate_csi_trans",
516-
CLK_SET_RATE_PARENT, 0xD4, 0, 5, CLK_DIVIDER_HIWORD_MASK, 0, },
516+
CLK_SET_RATE_PARENT, 0xD4, 0, 5, CLK_DIVIDER_HIWORD_MASK, },
517517
{ HI3670_CLK_DIV_DSI_TRANS, "clk_div_dsi_trans", "clk_gate_dsi_trans",
518-
CLK_SET_RATE_PARENT, 0xD4, 10, 5, CLK_DIVIDER_HIWORD_MASK, 0, },
518+
CLK_SET_RATE_PARENT, 0xD4, 10, 5, CLK_DIVIDER_HIWORD_MASK, },
519519
{ HI3670_CLK_DIV_PTP, "clk_div_ptp", "clk_andgt_ptp",
520-
CLK_SET_RATE_PARENT, 0xD8, 0, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
520+
CLK_SET_RATE_PARENT, 0xD8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
521521
{ HI3670_CLK_DIV_CLKOUT0_PLL, "clk_div_clkout0_pll", "clk_andgt_out0",
522-
CLK_SET_RATE_PARENT, 0xe0, 4, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
522+
CLK_SET_RATE_PARENT, 0xe0, 4, 6, CLK_DIVIDER_HIWORD_MASK, },
523523
{ HI3670_CLK_DIV_CLKOUT1_PLL, "clk_div_clkout1_pll", "clk_andgt_out1",
524-
CLK_SET_RATE_PARENT, 0xe0, 10, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
524+
CLK_SET_RATE_PARENT, 0xe0, 10, 6, CLK_DIVIDER_HIWORD_MASK, },
525525
{ HI3670_CLKDIV_DP_AUDIO_PLL_AO, "clkdiv_dp_audio_pll_ao", "clkgt_dp_audio_pll_ao",
526-
CLK_SET_RATE_PARENT, 0xBC, 11, 4, CLK_DIVIDER_HIWORD_MASK, 0, },
526+
CLK_SET_RATE_PARENT, 0xBC, 11, 4, CLK_DIVIDER_HIWORD_MASK, },
527527
{ HI3670_CLK_DIV_VDEC, "clk_div_vdec", "clk_andgt_vdec",
528-
CLK_SET_RATE_PARENT, 0xC4, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
528+
CLK_SET_RATE_PARENT, 0xC4, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
529529
{ HI3670_CLK_DIV_VENC, "clk_div_venc", "clk_andgt_venc",
530-
CLK_SET_RATE_PARENT, 0xC0, 8, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
530+
CLK_SET_RATE_PARENT, 0xC0, 8, 6, CLK_DIVIDER_HIWORD_MASK, },
531531
{ HI3670_CLK_ISP_SNCLK_DIV0, "clk_isp_snclk_div0", "clk_isp_snclk_fac",
532-
CLK_SET_RATE_PARENT, 0x108, 0, 2, CLK_DIVIDER_HIWORD_MASK, 0, },
532+
CLK_SET_RATE_PARENT, 0x108, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
533533
{ HI3670_CLK_ISP_SNCLK_DIV1, "clk_isp_snclk_div1", "clk_isp_snclk_fac",
534-
CLK_SET_RATE_PARENT, 0x10C, 14, 2, CLK_DIVIDER_HIWORD_MASK, 0, },
534+
CLK_SET_RATE_PARENT, 0x10C, 14, 2, CLK_DIVIDER_HIWORD_MASK, },
535535
{ HI3670_CLK_ISP_SNCLK_DIV2, "clk_isp_snclk_div2", "clk_isp_snclk_fac",
536-
CLK_SET_RATE_PARENT, 0x10C, 11, 2, CLK_DIVIDER_HIWORD_MASK, 0, },
536+
CLK_SET_RATE_PARENT, 0x10C, 11, 2, CLK_DIVIDER_HIWORD_MASK, },
537537
{ HI3670_CLK_DIV_ICS, "clk_div_ics", "clk_andgt_ics",
538-
CLK_SET_RATE_PARENT, 0xE4, 9, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
538+
CLK_SET_RATE_PARENT, 0xE4, 9, 6, CLK_DIVIDER_HIWORD_MASK, },
539539
};
540540

541541
/* clk_pmuctrl */
@@ -608,12 +608,12 @@ static const struct hisi_gate_clock hi3670_sctrl_gate_sep_clks[] = {
608608

609609
static const struct hisi_gate_clock hi3670_sctrl_gate_clks[] = {
610610
{ HI3670_CLK_ANDGT_IOPERI, "clk_andgt_ioperi", "clk_ppll0",
611-
CLK_SET_RATE_PARENT, 0x270, 6, CLK_GATE_HIWORD_MASK, 0, },
611+
CLK_SET_RATE_PARENT, 0x270, 6, CLK_GATE_HIWORD_MASK, },
612612
{ HI3670_CLKANDGT_ASP_SUBSYS_PERI, "clkandgt_asp_subsys_peri",
613613
"clk_ppll0",
614-
CLK_SET_RATE_PARENT, 0x268, 3, CLK_GATE_HIWORD_MASK, 0, },
614+
CLK_SET_RATE_PARENT, 0x268, 3, CLK_GATE_HIWORD_MASK, },
615615
{ HI3670_CLK_ANGT_ASP_SUBSYS, "clk_angt_asp_subsys", "clk_ppll0",
616-
CLK_SET_RATE_PARENT, 0x258, 0, CLK_GATE_HIWORD_MASK, 0, },
616+
CLK_SET_RATE_PARENT, 0x258, 0, CLK_GATE_HIWORD_MASK, },
617617
};
618618

619619
static const char *const
@@ -650,19 +650,19 @@ static const struct hisi_mux_clock hi3670_sctrl_mux_clks[] = {
650650

651651
static const struct hisi_divider_clock hi3670_sctrl_divider_clks[] = {
652652
{ HI3670_CLK_DIV_AOBUS, "clk_div_aobus", "clk_ppll0",
653-
CLK_SET_RATE_PARENT, 0x254, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
653+
CLK_SET_RATE_PARENT, 0x254, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
654654
{ HI3670_CLK_DIV_UFS_SUBSYS, "clk_div_ufs_subsys", "clk_mux_ufs_subsys",
655-
CLK_SET_RATE_PARENT, 0x274, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
655+
CLK_SET_RATE_PARENT, 0x274, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
656656
{ HI3670_CLK_DIV_IOPERI, "clk_div_ioperi", "clk_andgt_ioperi",
657-
CLK_SET_RATE_PARENT, 0x270, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
657+
CLK_SET_RATE_PARENT, 0x270, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
658658
{ HI3670_CLK_DIV_CLKOUT0_TCXO, "clk_div_clkout0_tcxo", "clkin_sys",
659-
CLK_SET_RATE_PARENT, 0x254, 6, 3, CLK_DIVIDER_HIWORD_MASK, 0, },
659+
CLK_SET_RATE_PARENT, 0x254, 6, 3, CLK_DIVIDER_HIWORD_MASK, },
660660
{ HI3670_CLK_DIV_CLKOUT1_TCXO, "clk_div_clkout1_tcxo", "clkin_sys",
661-
CLK_SET_RATE_PARENT, 0x254, 9, 3, CLK_DIVIDER_HIWORD_MASK, 0, },
661+
CLK_SET_RATE_PARENT, 0x254, 9, 3, CLK_DIVIDER_HIWORD_MASK, },
662662
{ HI3670_CLK_ASP_SUBSYS_PERI_DIV, "clk_asp_subsys_peri_div", "clkandgt_asp_subsys_peri",
663-
CLK_SET_RATE_PARENT, 0x268, 0, 3, CLK_DIVIDER_HIWORD_MASK, 0, },
663+
CLK_SET_RATE_PARENT, 0x268, 0, 3, CLK_DIVIDER_HIWORD_MASK, },
664664
{ HI3670_CLK_DIV_ASP_SUBSYS, "clk_div_asp_subsys", "clk_angt_asp_subsys",
665-
CLK_SET_RATE_PARENT, 0x250, 0, 3, CLK_DIVIDER_HIWORD_MASK, 0, },
665+
CLK_SET_RATE_PARENT, 0x250, 0, 3, CLK_DIVIDER_HIWORD_MASK, },
666666
};
667667

668668
/* clk_iomcu */
@@ -732,17 +732,17 @@ static const struct hisi_gate_clock hi3670_media1_gate_sep_clks[] = {
732732

733733
static const struct hisi_gate_clock hi3670_media1_gate_clks[] = {
734734
{ HI3670_CLK_GATE_VIVOBUS_ANDGT, "clk_gate_vivobus_andgt", "clk_mux_vivobus",
735-
CLK_SET_RATE_PARENT, 0x84, 3, CLK_GATE_HIWORD_MASK, 0, },
735+
CLK_SET_RATE_PARENT, 0x84, 3, CLK_GATE_HIWORD_MASK, },
736736
{ HI3670_CLK_ANDGT_EDC0, "clk_andgt_edc0", "clk_mux_edc0",
737-
CLK_SET_RATE_PARENT, 0x84, 7, CLK_GATE_HIWORD_MASK, 0, },
737+
CLK_SET_RATE_PARENT, 0x84, 7, CLK_GATE_HIWORD_MASK, },
738738
{ HI3670_CLK_ANDGT_LDI0, "clk_andgt_ldi0", "clk_mux_ldi0",
739-
CLK_SET_RATE_PARENT, 0x84, 9, CLK_GATE_HIWORD_MASK, 0, },
739+
CLK_SET_RATE_PARENT, 0x84, 9, CLK_GATE_HIWORD_MASK, },
740740
{ HI3670_CLK_ANDGT_LDI1, "clk_andgt_ldi1", "clk_mux_ldi1",
741-
CLK_SET_RATE_PARENT, 0x84, 8, CLK_GATE_HIWORD_MASK, 0, },
741+
CLK_SET_RATE_PARENT, 0x84, 8, CLK_GATE_HIWORD_MASK, },
742742
{ HI3670_CLK_MMBUF_PLL_ANDGT, "clk_mmbuf_pll_andgt", "clk_sw_mmbuf",
743-
CLK_SET_RATE_PARENT, 0x84, 14, CLK_GATE_HIWORD_MASK, 0, },
743+
CLK_SET_RATE_PARENT, 0x84, 14, CLK_GATE_HIWORD_MASK, },
744744
{ HI3670_PCLK_MMBUF_ANDGT, "pclk_mmbuf_andgt", "aclk_div_mmbuf",
745-
CLK_SET_RATE_PARENT, 0x84, 15, CLK_GATE_HIWORD_MASK, 0, },
745+
CLK_SET_RATE_PARENT, 0x84, 15, CLK_GATE_HIWORD_MASK, },
746746
};
747747

748748
static const char *const
@@ -799,17 +799,17 @@ static const struct hisi_mux_clock hi3670_media1_mux_clks[] = {
799799

800800
static const struct hisi_divider_clock hi3670_media1_divider_clks[] = {
801801
{ HI3670_CLK_DIV_VIVOBUS, "clk_div_vivobus", "clk_gate_vivobus_andgt",
802-
CLK_SET_RATE_PARENT, 0x74, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
802+
CLK_SET_RATE_PARENT, 0x74, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
803803
{ HI3670_CLK_DIV_EDC0, "clk_div_edc0", "clk_andgt_edc0",
804-
CLK_SET_RATE_PARENT, 0x68, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
804+
CLK_SET_RATE_PARENT, 0x68, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
805805
{ HI3670_CLK_DIV_LDI0, "clk_div_ldi0", "clk_andgt_ldi0",
806-
CLK_SET_RATE_PARENT, 0x60, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
806+
CLK_SET_RATE_PARENT, 0x60, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
807807
{ HI3670_CLK_DIV_LDI1, "clk_div_ldi1", "clk_andgt_ldi1",
808-
CLK_SET_RATE_PARENT, 0x64, 0, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
808+
CLK_SET_RATE_PARENT, 0x64, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
809809
{ HI3670_ACLK_DIV_MMBUF, "aclk_div_mmbuf", "clk_mmbuf_pll_andgt",
810-
CLK_SET_RATE_PARENT, 0x7C, 10, 6, CLK_DIVIDER_HIWORD_MASK, 0, },
810+
CLK_SET_RATE_PARENT, 0x7C, 10, 6, CLK_DIVIDER_HIWORD_MASK, },
811811
{ HI3670_PCLK_DIV_MMBUF, "pclk_div_mmbuf", "pclk_mmbuf_andgt",
812-
CLK_SET_RATE_PARENT, 0x78, 0, 2, CLK_DIVIDER_HIWORD_MASK, 0, },
812+
CLK_SET_RATE_PARENT, 0x78, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
813813
};
814814

815815
/* clk_media2 */

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