@@ -1787,14 +1787,25 @@ EXPORT_PER_CPU_SYMBOL(__preempt_count);
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DEFINE_PER_CPU (unsigned long, cpu_current_top_of_stack ) = TOP_OF_INIT_STACK ;
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+ static void wrmsrl_cstar (unsigned long val )
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+ {
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+ /*
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+ * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR
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+ * is so far ignored by the CPU, but raises a #VE trap in a TDX
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+ * guest. Avoid the pointless write on all Intel CPUs.
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+ */
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+ if (boot_cpu_data .x86_vendor != X86_VENDOR_INTEL )
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+ wrmsrl (MSR_CSTAR , val );
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+ }
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+
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/* May not be marked __init: used by software suspend */
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void syscall_init (void )
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{
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wrmsr (MSR_STAR , 0 , (__USER32_CS << 16 ) | __KERNEL_CS );
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wrmsrl (MSR_LSTAR , (unsigned long )entry_SYSCALL_64 );
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#ifdef CONFIG_IA32_EMULATION
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- wrmsrl ( MSR_CSTAR , (unsigned long )entry_SYSCALL_compat );
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+ wrmsrl_cstar ( (unsigned long )entry_SYSCALL_compat );
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/*
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* This only works on Intel CPUs.
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* On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
@@ -1806,7 +1817,7 @@ void syscall_init(void)
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(unsigned long )(cpu_entry_stack (smp_processor_id ()) + 1 ));
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wrmsrl_safe (MSR_IA32_SYSENTER_EIP , (u64 )entry_SYSENTER_compat );
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#else
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- wrmsrl ( MSR_CSTAR , (unsigned long )ignore_sysret );
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+ wrmsrl_cstar ( (unsigned long )ignore_sysret );
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wrmsrl_safe (MSR_IA32_SYSENTER_CS , (u64 )GDT_ENTRY_INVALID_SEG );
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wrmsrl_safe (MSR_IA32_SYSENTER_ESP , 0ULL );
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wrmsrl_safe (MSR_IA32_SYSENTER_EIP , 0ULL );
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