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spi: stm32: fix stm32_spi_prepare_mbr in case of odd clk_rate
Fix spi->clk_rate when it is odd to the nearest lowest even value because minimum SPI divider is 2. Signed-off-by: Amelie Delaunay <[email protected]> Signed-off-by: Alain Volmat <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
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drivers/spi/spi-stm32.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -441,7 +441,8 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
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{
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u32 div, mbrdiv;
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div = DIV_ROUND_UP(spi->clk_rate, speed_hz);
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/* Ensure spi->clk_rate is even */
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div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz);
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/*
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* SPI framework set xfer->speed_hz to master->max_speed_hz if

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