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Merge tag 'intel-pinctrl-v5.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into fixes
intel-pinctrl for v5.7-2 * Enable pin configuration setting for Baytrail * Fix interrupt handling due to hardware sighting for Cherryview * Fix PAD lock offset for Sunrisepoint-H The following is an automated git shortlog grouped by driver: baytrail: - Enable pin configuration setting for GPIO chip cherryview: - Add missing spinlock usage in chv_gpio_irq_handler sunrisepoint: - Fix PAD lock register offset for SPT-H
2 parents 90bcb0c + 69388e1 commit 9cd3472

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+13
-7
lines changed

3 files changed

+13
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lines changed

drivers/pinctrl/intel/pinctrl-baytrail.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1286,6 +1286,7 @@ static const struct gpio_chip byt_gpio_chip = {
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.direction_output = byt_gpio_direction_output,
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.get = byt_gpio_get,
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.set = byt_gpio_set,
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.set_config = gpiochip_generic_config,
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.dbg_show = byt_gpio_dbg_show,
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};
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drivers/pinctrl/intel/pinctrl-cherryview.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1479,11 +1479,15 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
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struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned long pending;
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unsigned long flags;
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u32 intr_line;
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chained_irq_enter(chip, desc);
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raw_spin_lock_irqsave(&chv_lock, flags);
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pending = readl(pctrl->regs + CHV_INTSTAT);
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
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unsigned int irq, offset;
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drivers/pinctrl/intel/pinctrl-sunrisepoint.c

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -15,17 +15,18 @@
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#include "pinctrl-intel.h"
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18-
#define SPT_PAD_OWN 0x020
19-
#define SPT_PADCFGLOCK 0x0a0
20-
#define SPT_HOSTSW_OWN 0x0d0
21-
#define SPT_GPI_IS 0x100
22-
#define SPT_GPI_IE 0x120
18+
#define SPT_PAD_OWN 0x020
19+
#define SPT_H_PADCFGLOCK 0x090
20+
#define SPT_LP_PADCFGLOCK 0x0a0
21+
#define SPT_HOSTSW_OWN 0x0d0
22+
#define SPT_GPI_IS 0x100
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#define SPT_GPI_IE 0x120
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#define SPT_COMMUNITY(b, s, e) \
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{ \
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.barno = (b), \
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.padown_offset = SPT_PAD_OWN, \
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.padcfglock_offset = SPT_PADCFGLOCK, \
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.padcfglock_offset = SPT_LP_PADCFGLOCK, \
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.hostown_offset = SPT_HOSTSW_OWN, \
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.is_offset = SPT_GPI_IS, \
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.ie_offset = SPT_GPI_IE, \
@@ -47,7 +48,7 @@
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{ \
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.barno = (b), \
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.padown_offset = SPT_PAD_OWN, \
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.padcfglock_offset = SPT_PADCFGLOCK, \
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.padcfglock_offset = SPT_H_PADCFGLOCK, \
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.hostown_offset = SPT_HOSTSW_OWN, \
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.is_offset = SPT_GPI_IS, \
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.ie_offset = SPT_GPI_IE, \

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