@@ -1028,6 +1028,9 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
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regmap_update_bits (hdptx -> regmap , CMN_REG (0086 ), PLL_PCG_POSTDIV_SEL_MASK ,
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FIELD_PREP (PLL_PCG_POSTDIV_SEL_MASK , cfg -> pms_sdiv ));
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+ regmap_update_bits (hdptx -> regmap , CMN_REG (0086 ), PLL_PCG_CLK_SEL_MASK ,
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+ FIELD_PREP (PLL_PCG_CLK_SEL_MASK , (hdptx -> hdmi_cfg .bpc - 8 ) >> 1 ));
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+
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regmap_update_bits (hdptx -> regmap , CMN_REG (0086 ), PLL_PCG_CLK_EN_MASK ,
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FIELD_PREP (PLL_PCG_CLK_EN_MASK , 0x1 ));
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@@ -1427,7 +1430,8 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
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hdptx -> hdmi_cfg .tmds_char_rate *= 100 ;
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}
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- dev_dbg (hdptx -> dev , "%s rate=%llu\n" , __func__ , hdptx -> hdmi_cfg .tmds_char_rate );
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+ dev_dbg (hdptx -> dev , "%s rate=%llu bpc=%u\n" , __func__ ,
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+ hdptx -> hdmi_cfg .tmds_char_rate , hdptx -> hdmi_cfg .bpc );
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}
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ret = rk_hdptx_phy_consumer_get (hdptx );
@@ -1492,6 +1496,19 @@ static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx,
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!rk_hdptx_phy_clk_pll_calc (hdmi -> tmds_char_rate , NULL ))
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return - EINVAL ;
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+ if (!hdmi -> bpc )
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+ hdmi -> bpc = 8 ;
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+
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+ switch (hdmi -> bpc ) {
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+ case 8 :
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+ case 10 :
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+ case 12 :
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+ case 16 :
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+ break ;
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+ default :
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+ return - EINVAL ;
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+ };
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+
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return 0 ;
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}
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@@ -1764,6 +1781,9 @@ static int rk_hdptx_phy_configure(struct phy *phy, union phy_configure_opts *opt
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hdptx -> hdmi_cfg = opts -> hdmi ;
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hdptx -> restrict_rate_change = true;
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}
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+
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+ dev_dbg (hdptx -> dev , "%s rate=%llu bpc=%u\n" , __func__ ,
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+ hdptx -> hdmi_cfg .tmds_char_rate , hdptx -> hdmi_cfg .bpc );
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return ret ;
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}
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@@ -1972,6 +1992,7 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev)
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return - ENOMEM ;
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hdptx -> dev = dev ;
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+ hdptx -> hdmi_cfg .bpc = 8 ;
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regs = devm_platform_get_and_ioremap_resource (pdev , 0 , & res );
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if (IS_ERR (regs ))
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