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139 | 139 | #define IEN(off) (0x1800 + (off) * 8)
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140 | 140 | #define PUPD(off) (0x1C00 + (off) * 8)
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141 | 141 | #define ISEL(off) (0x2C00 + (off) * 8)
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| 142 | +#define NOD(off) (0x3000 + (off) * 8) |
142 | 143 | #define SD_CH(off, ch) ((off) + (ch) * 4)
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143 | 144 | #define ETH_POC(off, ch) ((off) + (ch) * 4)
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144 | 145 | #define QSPI (0x3008)
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160 | 161 | #define IOLH_MASK 0x03
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161 | 162 | #define SR_MASK 0x01
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162 | 163 | #define PUPD_MASK 0x03
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| 164 | +#define NOD_MASK 0x01 |
163 | 165 |
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164 | 166 | #define PM_INPUT 0x1
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165 | 167 | #define PM_OUTPUT 0x2
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@@ -1338,6 +1340,18 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
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1338 | 1340 | break;
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1339 | 1341 | }
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1340 | 1342 |
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| 1343 | + case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
| 1344 | + case PIN_CONFIG_DRIVE_PUSH_PULL: |
| 1345 | + if (!(cfg & PIN_CFG_NOD)) |
| 1346 | + return -EINVAL; |
| 1347 | + |
| 1348 | + arg = rzg2l_read_pin_config(pctrl, NOD(off), bit, NOD_MASK); |
| 1349 | + if (!arg && param != PIN_CONFIG_DRIVE_PUSH_PULL) |
| 1350 | + return -EINVAL; |
| 1351 | + if (arg && param != PIN_CONFIG_DRIVE_OPEN_DRAIN) |
| 1352 | + return -EINVAL; |
| 1353 | + break; |
| 1354 | + |
1341 | 1355 | case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
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1342 | 1356 | if (!(cfg & PIN_CFG_IOLH_RZV2H))
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1343 | 1357 | return -EINVAL;
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@@ -1467,6 +1481,15 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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1467 | 1481 | rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
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1468 | 1482 | break;
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1469 | 1483 |
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| 1484 | + case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
| 1485 | + case PIN_CONFIG_DRIVE_PUSH_PULL: |
| 1486 | + if (!(cfg & PIN_CFG_NOD)) |
| 1487 | + return -EINVAL; |
| 1488 | + |
| 1489 | + rzg2l_rmw_pin_config(pctrl, NOD(off), bit, NOD_MASK, |
| 1490 | + param == PIN_CONFIG_DRIVE_OPEN_DRAIN ? 1 : 0); |
| 1491 | + break; |
| 1492 | + |
1470 | 1493 | case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
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1471 | 1494 | if (!(cfg & PIN_CFG_IOLH_RZV2H))
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1472 | 1495 | return -EINVAL;
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