ARM: dts: aspeed: asrock: Correct firmware flash SPI clocks

While I'm not aware of any problems that have occurred running these
at 100 MHz, the official word from ASRock is that 50 MHz is the
correct speed to use, so let's be safe and use that instead.

Signed-off-by: Zev Weiss <[email protected]>
Cc: [email protected]
Fixes: 2b81613 ("ARM: dts: aspeed: Add ASRock E3C246D4I BMC")
Fixes: a9a3d60 ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC")
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Joel Stanley <[email protected]>

Author: zevweiss

arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts

@@ -63,7 +63,7 @@
 		status = "okay";
 		m25p,fast-read;
 		label = "bmc";
-		spi-max-frequency = <100000000>; /* 100 MHz */
+		spi-max-frequency = <50000000>; /* 50 MHz */
 #include "openbmc-flash-layout.dtsi"
 	};
 };

arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts

@@ -51,7 +51,7 @@
 		status = "okay";
 		m25p,fast-read;
 		label = "bmc";
-		spi-max-frequency = <100000000>; /* 100 MHz */
+		spi-max-frequency = <50000000>; /* 50 MHz */
 #include "openbmc-flash-layout-64.dtsi"
 	};
 };