@@ -177,6 +177,16 @@ static const struct mtk_iommu_iova_region single_domain[] = {
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{.iova_base = 0 , .size = SZ_4G },
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};
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+ static const struct mtk_iommu_iova_region mt8192_multi_dom [] = {
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+ { .iova_base = 0x0 , .size = SZ_4G }, /* disp: 0 ~ 4G */
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+ #if IS_ENABLED (CONFIG_ARCH_DMA_ADDR_T_64BIT )
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+ { .iova_base = SZ_4G , .size = SZ_4G }, /* vdec: 4G ~ 8G */
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+ { .iova_base = SZ_4G * 2 , .size = SZ_4G }, /* CAM/MDP: 8G ~ 12G */
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+ { .iova_base = 0x240000000ULL , .size = 0x4000000 }, /* CCU0 */
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+ { .iova_base = 0x244000000ULL , .size = 0x4000000 }, /* CCU1 */
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+ #endif
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+ };
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+
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/*
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* There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
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* for the performance.
@@ -1038,12 +1048,24 @@ static const struct mtk_iommu_plat_data mt8183_data = {
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.larbid_remap = {{0 }, {4 }, {5 }, {6 }, {7 }, {2 }, {3 }, {1 }},
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};
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+ static const struct mtk_iommu_plat_data mt8192_data = {
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+ .m4u_plat = M4U_MT8192 ,
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+ .flags = HAS_BCLK | HAS_SUB_COMM | OUT_ORDER_WR_EN |
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+ WR_THROT_EN | IOVA_34_EN ,
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+ .inv_sel_reg = REG_MMU_INV_SEL_GEN2 ,
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+ .iova_region = mt8192_multi_dom ,
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+ .iova_region_nr = ARRAY_SIZE (mt8192_multi_dom ),
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+ .larbid_remap = {{0 }, {1 }, {4 , 5 }, {7 }, {2 }, {9 , 11 , 19 , 20 },
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+ {0 , 14 , 16 }, {0 , 13 , 18 , 17 }},
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+ };
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+
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static const struct of_device_id mtk_iommu_of_ids [] = {
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{ .compatible = "mediatek,mt2712-m4u" , .data = & mt2712_data },
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{ .compatible = "mediatek,mt6779-m4u" , .data = & mt6779_data },
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{ .compatible = "mediatek,mt8167-m4u" , .data = & mt8167_data },
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{ .compatible = "mediatek,mt8173-m4u" , .data = & mt8173_data },
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{ .compatible = "mediatek,mt8183-m4u" , .data = & mt8183_data },
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+ { .compatible = "mediatek,mt8192-m4u" , .data = & mt8192_data },
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{}
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};
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