Skip to content

Commit 9e6b815

Browse files
arndbarndb
committed
Merge tag 'riscv-cache-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
RISC-V cache drivers for v6.11 StarFive: A new driver for the cache controller on the jh8100, which didn't implement Zicbom and thus needs an implementation of non-standard cache management operations. Signed-off-by: Conor Dooley <[email protected]> * tag 'riscv-cache-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: MAINTAINERS: add microchip soc binding directory to microchip soc driver entry MAINTAINERS: add cache binding directory to cache driver entry cache: Add StarFive StarLink cache management dt-bindings: cache: Add docs for StarFive Starlink cache controller Link: https://lore.kernel.org/r/20240707-whoever-undesired-c5f6e96ae403@spud Signed-off-by: Arnd Bergmann <[email protected]>
2 parents a4dd55f + 3d41249 commit 9e6b815

File tree

5 files changed

+210
-2
lines changed

5 files changed

+210
-2
lines changed

‎Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml

Lines changed: 66 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,66 @@
1+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/cache/starfive,jh8100-starlink-cache.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: StarFive StarLink Cache Controller
8+
9+
maintainers:
10+
- Joshua Yeong <[email protected]>
11+
12+
description:
13+
StarFive's StarLink Cache Controller manages the L3 cache shared between
14+
clusters of CPU cores. The cache driver enables RISC-V non-standard cache
15+
management as an alternative to instructions in the RISC-V Zicbom extension.
16+
17+
allOf:
18+
- $ref: /schemas/cache-controller.yaml#
19+
20+
# We need a select here so we don't match all nodes with 'cache'
21+
select:
22+
properties:
23+
compatible:
24+
contains:
25+
enum:
26+
- starfive,jh8100-starlink-cache
27+
28+
required:
29+
- compatible
30+
31+
properties:
32+
compatible:
33+
items:
34+
- const: starfive,jh8100-starlink-cache
35+
- const: cache
36+
37+
reg:
38+
maxItems: 1
39+
40+
unevaluatedProperties: false
41+
42+
required:
43+
- compatible
44+
- reg
45+
- cache-block-size
46+
- cache-level
47+
- cache-sets
48+
- cache-size
49+
- cache-unified
50+
51+
examples:
52+
- |
53+
soc {
54+
#address-cells = <2>;
55+
#size-cells = <2>;
56+
57+
cache-controller@15000000 {
58+
compatible = "starfive,jh8100-starlink-cache", "cache";
59+
reg = <0x0 0x15000000 0x0 0x278>;
60+
cache-block-size = <64>;
61+
cache-level = <3>;
62+
cache-sets = <8192>;
63+
cache-size = <0x400000>;
64+
cache-unified;
65+
};
66+
};

‎MAINTAINERS

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14852,6 +14852,7 @@ MICROCHIP SOC DRIVERS
1485214852
M: Conor Dooley <[email protected]>
1485314853
S: Supported
1485414854
T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
14855+
F: Documentation/devicetree/bindings/soc/microchip/
1485514856
F: drivers/soc/microchip/
1485614857

1485714858
MICROCHIP SPI DRIVER
@@ -21287,6 +21288,7 @@ M: Conor Dooley <[email protected]>
2128721288
L: [email protected]
2128821289
S: Maintained
2128921290
T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
21291+
F: Documentation/devicetree/bindings/cache/
2129021292
F: drivers/cache
2129121293

2129221294
STARFIRE/DURALAN NETWORK DRIVER

‎drivers/cache/Kconfig

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,4 +14,13 @@ config SIFIVE_CCACHE
1414
help
1515
Support for the composable cache controller on SiFive platforms.
1616

17+
config STARFIVE_STARLINK_CACHE
18+
bool "StarFive StarLink Cache controller"
19+
depends on RISCV
20+
depends on ARCH_STARFIVE
21+
select RISCV_DMA_NONCOHERENT
22+
select RISCV_NONSTANDARD_CACHE_OPS
23+
help
24+
Support for the StarLink cache controller IP from StarFive.
25+
1726
endmenu

‎drivers/cache/Makefile

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
# SPDX-License-Identifier: GPL-2.0
22

3-
obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o
4-
obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o
3+
obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o
4+
obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o
5+
obj-$(CONFIG_STARFIVE_STARLINK_CACHE) += starfive_starlink_cache.o

‎drivers/cache/starfive_starlink_cache.c

Lines changed: 130 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,130 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* Cache Management Operations for StarFive's Starlink cache controller
4+
*
5+
* Copyright (C) 2024 Shanghai StarFive Technology Co., Ltd.
6+
*
7+
* Author: Joshua Yeong <[email protected]>
8+
*/
9+
10+
#include <linux/bitfield.h>
11+
#include <linux/cacheflush.h>
12+
#include <linux/iopoll.h>
13+
#include <linux/of_address.h>
14+
15+
#include <asm/dma-noncoherent.h>
16+
17+
#define STARLINK_CACHE_FLUSH_START_ADDR 0x0
18+
#define STARLINK_CACHE_FLUSH_END_ADDR 0x8
19+
#define STARLINK_CACHE_FLUSH_CTL 0x10
20+
#define STARLINK_CACHE_ALIGN 0x40
21+
22+
#define STARLINK_CACHE_ADDRESS_RANGE_MASK GENMASK(39, 0)
23+
#define STARLINK_CACHE_FLUSH_CTL_MODE_MASK GENMASK(2, 1)
24+
#define STARLINK_CACHE_FLUSH_CTL_ENABLE_MASK BIT(0)
25+
26+
#define STARLINK_CACHE_FLUSH_CTL_CLEAN_INVALIDATE 0
27+
#define STARLINK_CACHE_FLUSH_CTL_MAKE_INVALIDATE 1
28+
#define STARLINK_CACHE_FLUSH_CTL_CLEAN_SHARED 2
29+
#define STARLINK_CACHE_FLUSH_POLL_DELAY_US 1
30+
#define STARLINK_CACHE_FLUSH_TIMEOUT_US 5000000
31+
32+
static void __iomem *starlink_cache_base;
33+
34+
static void starlink_cache_flush_complete(void)
35+
{
36+
volatile void __iomem *ctl = starlink_cache_base + STARLINK_CACHE_FLUSH_CTL;
37+
u64 v;
38+
int ret;
39+
40+
ret = readq_poll_timeout_atomic(ctl, v, !(v & STARLINK_CACHE_FLUSH_CTL_ENABLE_MASK),
41+
STARLINK_CACHE_FLUSH_POLL_DELAY_US,
42+
STARLINK_CACHE_FLUSH_TIMEOUT_US);
43+
if (ret)
44+
WARN(1, "StarFive Starlink cache flush operation timeout\n");
45+
}
46+
47+
static void starlink_cache_dma_cache_wback(phys_addr_t paddr, unsigned long size)
48+
{
49+
writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr),
50+
starlink_cache_base + STARLINK_CACHE_FLUSH_START_ADDR);
51+
writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size),
52+
starlink_cache_base + STARLINK_CACHE_FLUSH_END_ADDR);
53+
54+
mb();
55+
writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK,
56+
STARLINK_CACHE_FLUSH_CTL_CLEAN_SHARED),
57+
starlink_cache_base + STARLINK_CACHE_FLUSH_CTL);
58+
59+
starlink_cache_flush_complete();
60+
}
61+
62+
static void starlink_cache_dma_cache_invalidate(phys_addr_t paddr, unsigned long size)
63+
{
64+
writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr),
65+
starlink_cache_base + STARLINK_CACHE_FLUSH_START_ADDR);
66+
writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size),
67+
starlink_cache_base + STARLINK_CACHE_FLUSH_END_ADDR);
68+
69+
mb();
70+
writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK,
71+
STARLINK_CACHE_FLUSH_CTL_MAKE_INVALIDATE),
72+
starlink_cache_base + STARLINK_CACHE_FLUSH_CTL);
73+
74+
starlink_cache_flush_complete();
75+
}
76+
77+
static void starlink_cache_dma_cache_wback_inv(phys_addr_t paddr, unsigned long size)
78+
{
79+
writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr),
80+
starlink_cache_base + STARLINK_CACHE_FLUSH_START_ADDR);
81+
writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size),
82+
starlink_cache_base + STARLINK_CACHE_FLUSH_END_ADDR);
83+
84+
mb();
85+
writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK,
86+
STARLINK_CACHE_FLUSH_CTL_CLEAN_INVALIDATE),
87+
starlink_cache_base + STARLINK_CACHE_FLUSH_CTL);
88+
89+
starlink_cache_flush_complete();
90+
}
91+
92+
static const struct riscv_nonstd_cache_ops starlink_cache_ops = {
93+
.wback = &starlink_cache_dma_cache_wback,
94+
.inv = &starlink_cache_dma_cache_invalidate,
95+
.wback_inv = &starlink_cache_dma_cache_wback_inv,
96+
};
97+
98+
static const struct of_device_id starlink_cache_ids[] = {
99+
{ .compatible = "starfive,jh8100-starlink-cache" },
100+
{ /* sentinel */ }
101+
};
102+
103+
static int __init starlink_cache_init(void)
104+
{
105+
struct device_node *np;
106+
u32 block_size;
107+
int ret;
108+
109+
np = of_find_matching_node(NULL, starlink_cache_ids);
110+
if (!of_device_is_available(np))
111+
return -ENODEV;
112+
113+
ret = of_property_read_u32(np, "cache-block-size", &block_size);
114+
if (ret)
115+
return ret;
116+
117+
if (block_size % STARLINK_CACHE_ALIGN)
118+
return -EINVAL;
119+
120+
starlink_cache_base = of_iomap(np, 0);
121+
if (!starlink_cache_base)
122+
return -ENOMEM;
123+
124+
riscv_cbom_block_size = block_size;
125+
riscv_noncoherent_supported();
126+
riscv_noncoherent_register_cache_ops(&starlink_cache_ops);
127+
128+
return 0;
129+
}
130+
arch_initcall(starlink_cache_init);

0 commit comments

Comments
 (0)