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AngeloGioacchino Del RegnoChun-Kuang Hu
AngeloGioacchino Del Regno
authored and
Chun-Kuang Hu
committed
drm/mediatek: mtk_dpi: Use an array for pixclk factor calculation
Setting the TVD PLL clock requires to multiply the target pixel clock by a specific constant factor to achieve the target PLL frequency, and this is done to reduce jitter to acceptable levels. On all MediaTek SoCs, the factor is not retrieved by any real kind of calculation but rather by checking if the target pixel clock is less than a specified frequency, hence assigning a function pointer for just a bunch of if branches does enlarge the code size for little reason. Remove all SoC-specific functions, add a structure `mtk_dpi_factor` that holds a clock frequency and corresponding PLL factor, and declare the constraints for each SoC in form of an array of said structure. Instead of function pointers, this structure (and its size) is then assigned to each SoC's platform data. The "calculation" is then performed with a new static function mtk_dpi_calculate_factor(dpi, mode_clk) that iterates through all of the entries of the aforementioned array and returns the right factor. If no factor is found, the lowest possible factor is returned, mimicking the same flow as all of the old per-SoC calculation functions. This commit brings no functional change. Reviewed-by: CK Hu <[email protected]> Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Link: https://patchwork.kernel.org/project/dri-devel/patch/[email protected]/ Signed-off-by: Chun-Kuang Hu <[email protected]>
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‎drivers/gpu/drm/mediatek/mtk_dpi.c

Lines changed: 52 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -118,9 +118,15 @@ struct mtk_dpi_yc_limit {
118118
u16 c_bottom;
119119
};
120120

121+
struct mtk_dpi_factor {
122+
u32 clock;
123+
u8 factor;
124+
};
125+
121126
/**
122127
* struct mtk_dpi_conf - Configuration of mediatek dpi.
123-
* @cal_factor: Callback function to calculate factor value.
128+
* @dpi_factor: SoC-specific pixel clock PLL factor values.
129+
* @num_dpi_factor: Number of pixel clock PLL factor values.
124130
* @reg_h_fre_con: Register address of frequency control.
125131
* @max_clock_khz: Max clock frequency supported for this SoCs in khz units.
126132
* @edge_sel_en: Enable of edge selection.
@@ -141,7 +147,8 @@ struct mtk_dpi_yc_limit {
141147
* @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
142148
*/
143149
struct mtk_dpi_conf {
144-
unsigned int (*cal_factor)(int clock);
150+
const struct mtk_dpi_factor *dpi_factor;
151+
const u8 num_dpi_factor;
145152
u32 reg_h_fre_con;
146153
u32 max_clock_khz;
147154
bool edge_sel_en;
@@ -516,6 +523,20 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
516523
return ret;
517524
}
518525

526+
static unsigned int mtk_dpi_calculate_factor(struct mtk_dpi *dpi, int mode_clk)
527+
{
528+
const struct mtk_dpi_factor *dpi_factor = dpi->conf->dpi_factor;
529+
int i;
530+
531+
for (i = 0; i < dpi->conf->num_dpi_factor; i++) {
532+
if (mode_clk <= dpi_factor[i].clock)
533+
return dpi_factor[i].factor;
534+
}
535+
536+
/* If no match try the lowest possible factor */
537+
return dpi_factor[dpi->conf->num_dpi_factor - 1].factor;
538+
}
539+
519540
static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
520541
struct drm_display_mode *mode)
521542
{
@@ -530,7 +551,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
530551
unsigned int factor;
531552

532553
/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
533-
factor = dpi->conf->cal_factor(mode->clock);
554+
factor = mtk_dpi_calculate_factor(dpi, mode->clock);
534555
drm_display_mode_to_videomode(mode, &vm);
535556
pll_rate = vm.pixelclock * factor;
536557

@@ -965,48 +986,6 @@ static const struct component_ops mtk_dpi_component_ops = {
965986
.unbind = mtk_dpi_unbind,
966987
};
967988

968-
static unsigned int mt8173_calculate_factor(int clock)
969-
{
970-
if (clock <= 27000)
971-
return 3 << 4;
972-
else if (clock <= 84000)
973-
return 3 << 3;
974-
else if (clock <= 167000)
975-
return 3 << 2;
976-
else
977-
return 3 << 1;
978-
}
979-
980-
static unsigned int mt2701_calculate_factor(int clock)
981-
{
982-
if (clock <= 64000)
983-
return 4;
984-
else if (clock <= 128000)
985-
return 2;
986-
else
987-
return 1;
988-
}
989-
990-
static unsigned int mt8183_calculate_factor(int clock)
991-
{
992-
if (clock <= 27000)
993-
return 8;
994-
else if (clock <= 167000)
995-
return 4;
996-
else
997-
return 2;
998-
}
999-
1000-
static unsigned int mt8195_dpintf_calculate_factor(int clock)
1001-
{
1002-
if (clock < 70000)
1003-
return 4;
1004-
else if (clock < 200000)
1005-
return 2;
1006-
else
1007-
return 1;
1008-
}
1009-
1010989
static const u32 mt8173_output_fmts[] = {
1011990
MEDIA_BUS_FMT_RGB888_1X24,
1012991
};
@@ -1021,8 +1000,25 @@ static const u32 mt8195_output_fmts[] = {
10211000
MEDIA_BUS_FMT_YUYV8_1X16,
10221001
};
10231002

1003+
static const struct mtk_dpi_factor dpi_factor_mt2701[] = {
1004+
{ 64000, 4 }, { 128000, 2 }, { U32_MAX, 1 }
1005+
};
1006+
1007+
static const struct mtk_dpi_factor dpi_factor_mt8173[] = {
1008+
{ 27000, 48 }, { 84000, 24 }, { 167000, 12 }, { U32_MAX, 6 }
1009+
};
1010+
1011+
static const struct mtk_dpi_factor dpi_factor_mt8183[] = {
1012+
{ 27000, 8 }, { 167000, 4 }, { U32_MAX, 2 }
1013+
};
1014+
1015+
static const struct mtk_dpi_factor dpi_factor_mt8195_dp_intf[] = {
1016+
{ 70000 - 1, 4 }, { 200000 - 1, 2 }, { U32_MAX, 1 }
1017+
};
1018+
10241019
static const struct mtk_dpi_conf mt8173_conf = {
1025-
.cal_factor = mt8173_calculate_factor,
1020+
.dpi_factor = dpi_factor_mt8173,
1021+
.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8173),
10261022
.reg_h_fre_con = 0xe0,
10271023
.max_clock_khz = 300000,
10281024
.output_fmts = mt8173_output_fmts,
@@ -1039,7 +1035,8 @@ static const struct mtk_dpi_conf mt8173_conf = {
10391035
};
10401036

10411037
static const struct mtk_dpi_conf mt2701_conf = {
1042-
.cal_factor = mt2701_calculate_factor,
1038+
.dpi_factor = dpi_factor_mt2701,
1039+
.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt2701),
10431040
.reg_h_fre_con = 0xb0,
10441041
.edge_sel_en = true,
10451042
.max_clock_khz = 150000,
@@ -1057,7 +1054,8 @@ static const struct mtk_dpi_conf mt2701_conf = {
10571054
};
10581055

10591056
static const struct mtk_dpi_conf mt8183_conf = {
1060-
.cal_factor = mt8183_calculate_factor,
1057+
.dpi_factor = dpi_factor_mt8183,
1058+
.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183),
10611059
.reg_h_fre_con = 0xe0,
10621060
.max_clock_khz = 100000,
10631061
.output_fmts = mt8183_output_fmts,
@@ -1074,7 +1072,8 @@ static const struct mtk_dpi_conf mt8183_conf = {
10741072
};
10751073

10761074
static const struct mtk_dpi_conf mt8186_conf = {
1077-
.cal_factor = mt8183_calculate_factor,
1075+
.dpi_factor = dpi_factor_mt8183,
1076+
.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183),
10781077
.reg_h_fre_con = 0xe0,
10791078
.max_clock_khz = 150000,
10801079
.output_fmts = mt8183_output_fmts,
@@ -1092,7 +1091,8 @@ static const struct mtk_dpi_conf mt8186_conf = {
10921091
};
10931092

10941093
static const struct mtk_dpi_conf mt8192_conf = {
1095-
.cal_factor = mt8183_calculate_factor,
1094+
.dpi_factor = dpi_factor_mt8183,
1095+
.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183),
10961096
.reg_h_fre_con = 0xe0,
10971097
.max_clock_khz = 150000,
10981098
.output_fmts = mt8183_output_fmts,
@@ -1109,7 +1109,8 @@ static const struct mtk_dpi_conf mt8192_conf = {
11091109
};
11101110

11111111
static const struct mtk_dpi_conf mt8195_dpintf_conf = {
1112-
.cal_factor = mt8195_dpintf_calculate_factor,
1112+
.dpi_factor = dpi_factor_mt8195_dp_intf,
1113+
.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8195_dp_intf),
11131114
.max_clock_khz = 600000,
11141115
.output_fmts = mt8195_output_fmts,
11151116
.num_output_fmts = ARRAY_SIZE(mt8195_output_fmts),

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