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i3c: master: svc: separate err, fifo and disable interrupt of reset function
Sometimes only need to reset err and fifo regs, so split the origin reset function to three functions. Put them at the top of the file, to let more functions can call them. Signed-off-by: Clark Wang <[email protected]> Reviewed-by: Miquel Raynal <[email protected]> Reviewed-by: Jun Li <[email protected]> Signed-off-by: Alexandre Belloni <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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drivers/i3c/master/svc-i3c-master.c

Lines changed: 34 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -236,6 +236,40 @@ static void svc_i3c_master_disable_interrupts(struct svc_i3c_master *master)
236236
writel(mask, master->regs + SVC_I3C_MINTCLR);
237237
}
238238

239+
static void svc_i3c_master_clear_merrwarn(struct svc_i3c_master *master)
240+
{
241+
/* Clear pending warnings */
242+
writel(readl(master->regs + SVC_I3C_MERRWARN),
243+
master->regs + SVC_I3C_MERRWARN);
244+
}
245+
246+
static void svc_i3c_master_flush_fifo(struct svc_i3c_master *master)
247+
{
248+
/* Flush FIFOs */
249+
writel(SVC_I3C_MDATACTRL_FLUSHTB | SVC_I3C_MDATACTRL_FLUSHRB,
250+
master->regs + SVC_I3C_MDATACTRL);
251+
}
252+
253+
static void svc_i3c_master_reset_fifo_trigger(struct svc_i3c_master *master)
254+
{
255+
u32 reg;
256+
257+
/* Set RX and TX tigger levels, flush FIFOs */
258+
reg = SVC_I3C_MDATACTRL_FLUSHTB |
259+
SVC_I3C_MDATACTRL_FLUSHRB |
260+
SVC_I3C_MDATACTRL_UNLOCK_TRIG |
261+
SVC_I3C_MDATACTRL_TXTRIG_FIFO_NOT_FULL |
262+
SVC_I3C_MDATACTRL_RXTRIG_FIFO_NOT_EMPTY;
263+
writel(reg, master->regs + SVC_I3C_MDATACTRL);
264+
}
265+
266+
static void svc_i3c_master_reset(struct svc_i3c_master *master)
267+
{
268+
svc_i3c_master_clear_merrwarn(master);
269+
svc_i3c_master_reset_fifo_trigger(master);
270+
svc_i3c_master_disable_interrupts(master);
271+
}
272+
239273
static inline struct svc_i3c_master *
240274
to_svc_i3c_master(struct i3c_master_controller *master)
241275
{
@@ -279,12 +313,6 @@ static void svc_i3c_master_emit_stop(struct svc_i3c_master *master)
279313
udelay(1);
280314
}
281315

282-
static void svc_i3c_master_clear_merrwarn(struct svc_i3c_master *master)
283-
{
284-
writel(readl(master->regs + SVC_I3C_MERRWARN),
285-
master->regs + SVC_I3C_MERRWARN);
286-
}
287-
288316
static int svc_i3c_master_handle_ibi(struct svc_i3c_master *master,
289317
struct i3c_dev_desc *dev)
290318
{
@@ -1334,25 +1362,6 @@ static const struct i3c_master_controller_ops svc_i3c_master_ops = {
13341362
.disable_ibi = svc_i3c_master_disable_ibi,
13351363
};
13361364

1337-
static void svc_i3c_master_reset(struct svc_i3c_master *master)
1338-
{
1339-
u32 reg;
1340-
1341-
/* Clear pending warnings */
1342-
writel(readl(master->regs + SVC_I3C_MERRWARN),
1343-
master->regs + SVC_I3C_MERRWARN);
1344-
1345-
/* Set RX and TX tigger levels, flush FIFOs */
1346-
reg = SVC_I3C_MDATACTRL_FLUSHTB |
1347-
SVC_I3C_MDATACTRL_FLUSHRB |
1348-
SVC_I3C_MDATACTRL_UNLOCK_TRIG |
1349-
SVC_I3C_MDATACTRL_TXTRIG_FIFO_NOT_FULL |
1350-
SVC_I3C_MDATACTRL_RXTRIG_FIFO_NOT_EMPTY;
1351-
writel(reg, master->regs + SVC_I3C_MDATACTRL);
1352-
1353-
svc_i3c_master_disable_interrupts(master);
1354-
}
1355-
13561365
static int svc_i3c_master_probe(struct platform_device *pdev)
13571366
{
13581367
struct device *dev = &pdev->dev;

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