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Merge tag 'tegra-for-5.8-media' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers
media: tegra: Changes for v5.8-rc1 This contains a V4L2 video capture driver for Tegra210. * tag 'tegra-for-5.8-media' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: media: tegra-video: Do not enable COMPILE_TEST MAINTAINERS: correct path in TEGRA VIDEO DRIVER media: tegra-video: Make tegra210_video_formats static MAINTAINERS: Add Tegra Video driver section media: tegra-video: Add Tegra210 Video input driver dt-bindings: i2c: tegra: Document Tegra210 VI I2C dt-bindings: tegra: Add VI and CSI bindings dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 dt-bindings: memory: tegra: Add external memory controller binding for Tegra210 dt-bindings: clock: tegra: Remove PMC clock IDs dt-bindings: clock: tegra: Add clock ID for CSI TPG clock Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
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‎Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt

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Binding for NVIDIA Tegra20 CPUFreq
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==================================
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Required properties:
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- clocks: Must contain an entry for the CPU clock.
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See ../clocks/clock-bindings.txt for details.
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- operating-points-v2: See ../bindings/opp/opp.txt for details.
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- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details.
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For each opp entry in 'operating-points-v2' table:
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- opp-supported-hw: Two bitfields indicating:
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On Tegra20:
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1. CPU process ID mask
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2. SoC speedo ID mask
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On Tegra30:
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1. CPU process ID mask
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2. CPU speedo ID mask
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A bitwise AND is performed against these values and if any bit
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matches, the OPP gets enabled.
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- opp-microvolt: CPU voltage triplet.
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Optional properties:
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- cpu-supply: Phandle to the CPU power supply.
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Example:
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regulators {
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cpu_reg: regulator0 {
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regulator-name = "vdd_cpu";
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};
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};
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cpu0_opp_table: opp_table0 {
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compatible = "operating-points-v2";
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opp@456000000 {
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clock-latency-ns = <125000>;
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opp-microvolt = <825000 825000 1125000>;
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opp-supported-hw = <0x03 0x0001>;
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opp-hz = /bits/ 64 <456000000>;
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};
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...
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};
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cpus {
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cpu@0 {
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compatible = "arm,cortex-a9";
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clocks = <&tegra_car TEGRA20_CLK_CCLK>;
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operating-points-v2 = <&cpu0_opp_table>;
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cpu-supply = <&cpu_reg>;
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#cooling-cells = <2>;
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};
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};

‎Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt

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@@ -40,14 +40,30 @@ of the following host1x client modules:
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Required properties:
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- compatible: "nvidia,tegra<chip>-vi"
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- reg: Physical base address and length of the controller's registers.
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- reg: Physical base address and length of the controller registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain one entry, for the module clock.
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- clocks: clocks: Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- vi
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- Tegra20/Tegra30/Tegra114/Tegra124:
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- vi
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- Tegra210:
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- power-domains: Must include venc powergate node as vi is in VE partition.
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- Tegra210 has CSI part of VI sharing same host interface and register space.
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So, VI device node should have CSI child node.
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- csi: mipi csi interface to vi
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Required properties:
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- compatible: "nvidia,tegra210-csi"
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- reg: Physical base address offset to parent and length of the controller
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registers.
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- clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks.
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See ../clocks/clock-bindings.txt for details.
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- power-domains: Must include sor powergate node as csicil is in
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SOR partition.
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- epp: encoder pre-processor
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reset-names = "mpe";
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};
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vi {
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compatible = "nvidia,tegra20-vi";
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reg = <0x54080000 0x00040000>;
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interrupts = <0 69 0x04>;
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clocks = <&tegra_car TEGRA20_CLK_VI>;
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resets = <&tegra_car 100>;
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reset-names = "vi";
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vi@54080000 {
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compatible = "nvidia,tegra210-vi";
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reg = <0x0 0x54080000 0x0 0x700>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
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assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
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clocks = <&tegra_car TEGRA210_CLK_VI>;
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power-domains = <&pd_venc>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x54080000 0x2000>;
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csi@838 {
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compatible = "nvidia,tegra210-csi";
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reg = <0x838 0x1300>;
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assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
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<&tegra_car TEGRA210_CLK_CILCD>,
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<&tegra_car TEGRA210_CLK_CILE>,
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<&tegra_car TEGRA210_CLK_CSI_TPG>;
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assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
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<&tegra_car TEGRA210_CLK_PLL_P>,
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<&tegra_car TEGRA210_CLK_PLL_P>;
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assigned-clock-rates = <102000000>,
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<102000000>,
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<102000000>,
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<972000000>;
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clocks = <&tegra_car TEGRA210_CLK_CSI>,
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<&tegra_car TEGRA210_CLK_CILAB>,
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<&tegra_car TEGRA210_CLK_CILCD>,
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<&tegra_car TEGRA210_CLK_CILE>,
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<&tegra_car TEGRA210_CLK_CSI_TPG>;
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clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
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power-domains = <&pd_sor>;
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};
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};
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epp {

‎Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt

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Due to above changes, Tegra114 I2C driver makes incompatible with
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previous hardware driver. Hence, tegra114 I2C controller is compatible
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with "nvidia,tegra114-i2c".
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nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is part of the
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host1x domain and typically used for camera use-cases. This VI I2C
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controller is mostly compatible with the programming model of the
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regular I2C controllers with a few exceptions. The I2C registers start
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at an offset of 0xc00 (instead of 0), registers are 16 bytes apart
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(rather than 4) and the controller does not support slave mode.
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- reg: Should contain I2C controller registers physical address and length.
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- interrupts: Should contain I2C controller interrupts.
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- address-cells: Address cells for I2C device address.

‎Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra210 SoC External Memory Controller
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maintainers:
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- Thierry Reding <[email protected]>
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- Jon Hunter <[email protected]>
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description: |
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The EMC interfaces with the off-chip SDRAM to service the request stream
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sent from the memory controller.
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properties:
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compatible:
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const: nvidia,tegra210-emc
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reg:
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maxItems: 3
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clocks:
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items:
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- description: external memory clock
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clock-names:
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items:
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- const: emc
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interrupts:
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items:
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- description: EMC general interrupt
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memory-region:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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phandle to a reserved memory region describing the table of EMC
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frequencies trained by the firmware
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nvidia,memory-controller:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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phandle of the memory controller node
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- nvidia,memory-controller
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/tegra210-car.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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emc_table: emc-table@83400000 {
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compatible = "nvidia,tegra210-emc-table";
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reg = <0x83400000 0x10000>;
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};
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};
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external-memory-controller@7001b000 {
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compatible = "nvidia,tegra210-emc";
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reg = <0x7001b000 0x1000>,
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<0x7001e000 0x1000>,
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<0x7001f000 0x1000>;
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clocks = <&tegra_car TEGRA210_CLK_EMC>;
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clock-names = "emc";
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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memory-region = <&emc_table>;
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nvidia,memory-controller = <&mc>;
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};

‎MAINTAINERS

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S: Supported
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F: drivers/spi/spi-tegra*
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TEGRA VIDEO DRIVER
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M: Thierry Reding <[email protected]>
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M: Jonathan Hunter <[email protected]>
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M: Sowjanya Komatineni <[email protected]>
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L: [email protected]
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L: [email protected]
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S: Maintained
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F: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
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F: drivers/staging/media/tegra-video/
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TEGRA XUSB PADCTL DRIVER
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M: JC Kuo <[email protected]>
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S: Supported

‎drivers/staging/media/Kconfig

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source "drivers/staging/media/tegra-vde/Kconfig"
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source "drivers/staging/media/tegra-video/Kconfig"
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source "drivers/staging/media/ipu3/Kconfig"
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source "drivers/staging/media/soc_camera/Kconfig"

‎drivers/staging/media/Makefile

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obj-$(CONFIG_VIDEO_MESON_VDEC) += meson/vdec/
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obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/
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obj-$(CONFIG_VIDEO_SUNXI) += sunxi/
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obj-$(CONFIG_VIDEO_TEGRA) += tegra-video/
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obj-$(CONFIG_TEGRA_VDE) += tegra-vde/
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obj-$(CONFIG_VIDEO_HANTRO) += hantro/
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obj-$(CONFIG_VIDEO_IPU3_IMGU) += ipu3/

‎drivers/staging/media/tegra-video/Kconfig

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# SPDX-License-Identifier: GPL-2.0-only
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config VIDEO_TEGRA
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tristate "NVIDIA Tegra VI driver"
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depends on TEGRA_HOST1X
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select VIDEO_V4L2
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select MEDIA_CONTROLLER
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select VIDEOBUF2_DMA_CONTIG
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help
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Choose this option if you have an NVIDIA Tegra SoC.
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To compile this driver as a module, choose M here: the module
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will be called tegra-video.

‎drivers/staging/media/tegra-video/Makefile

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# SPDX-License-Identifier: GPL-2.0
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tegra-video-objs := \
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video.o \
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vi.o \
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csi.o
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tegra-video-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
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obj-$(CONFIG_VIDEO_TEGRA) += tegra-video.o

‎drivers/staging/media/tegra-video/TODO

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TODO list
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* Currently driver supports Tegra build-in TPG only with direct media links
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from CSI to VI. Add kernel config CONFIG_VIDEO_TEGRA_TPG and update the
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driver to do TPG Vs Sensor media links based on CONFIG_VIDEO_TEGRA_TPG.
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* Add real camera sensor capture support.
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* Add Tegra CSI MIPI pads calibration.
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* Add MIPI clock Settle time computation based on the data rate.
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* Add support for Ganged mode.
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* Add RAW10 packed video format support to Tegra210 video formats.
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* Add support for suspend and resume.
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* Make sure v4l2-compliance tests pass with all of the above implementations.

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