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Merge tag 'socfpga_update_for_v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/soc
SoCFPGA update for v5.9, part 2 - Add missing put_device() call in socfpga base power management support * tag 'socfpga_update_for_v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: socfpga: PM: add missing put_device() call in socfpga_setup_ocram_self_refresh() ARM: dts: socfpga: add the temperature sensor to the Arria10 devkit arm: dts: socfpga: add reset-names to spi node arm64: dts: agilex: add nand clocks arm64: dts: agilex: populate clock dts entries for Intel SoCFPGA Agilex Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2 parents 552c0e3 + 3ad7b4e commit a04e84c

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7 files changed

+103
-3
lines changed

7 files changed

+103
-3
lines changed

‎arch/arm/boot/dts/socfpga.dtsi

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -829,6 +829,7 @@
829829
num-cs = <4>;
830830
clocks = <&spi_m_clk>;
831831
resets = <&rst SPIM0_RESET>;
832+
reset-names = "spi";
832833
status = "disabled";
833834
};
834835

@@ -841,6 +842,7 @@
841842
num-cs = <4>;
842843
clocks = <&spi_m_clk>;
843844
resets = <&rst SPIM1_RESET>;
845+
reset-names = "spi";
844846
status = "disabled";
845847
};
846848

‎arch/arm/boot/dts/socfpga_arria10.dtsi

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -613,6 +613,7 @@
613613
/*32bit_access;*/
614614
clocks = <&spi_m_clk>;
615615
resets = <&rst SPIM0_RESET>;
616+
reset-names = "spi";
616617
status = "disabled";
617618
};
618619

@@ -628,6 +629,7 @@
628629
rx-dma-channel = <&pdma 17>;
629630
clocks = <&spi_m_clk>;
630631
resets = <&rst SPIM1_RESET>;
632+
reset-names = "spi";
631633
status = "disabled";
632634
};
633635

‎arch/arm/boot/dts/socfpga_arria10_socdk.dtsi

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -162,6 +162,11 @@
162162
compatible = "ltc2977";
163163
reg = <0x5c>;
164164
};
165+
166+
temp@4c {
167+
compatible = "maxim,max1619";
168+
reg = <0x4c>;
169+
};
165170
};
166171

167172
&uart1 {

‎arch/arm/mach-socfpga/pm.c

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -49,14 +49,14 @@ static int socfpga_setup_ocram_self_refresh(void)
4949
if (!ocram_pool) {
5050
pr_warn("%s: ocram pool unavailable!\n", __func__);
5151
ret = -ENODEV;
52-
goto put_node;
52+
goto put_device;
5353
}
5454

5555
ocram_base = gen_pool_alloc(ocram_pool, socfpga_sdram_self_refresh_sz);
5656
if (!ocram_base) {
5757
pr_warn("%s: unable to alloc ocram!\n", __func__);
5858
ret = -ENOMEM;
59-
goto put_node;
59+
goto put_device;
6060
}
6161

6262
ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
@@ -67,7 +67,7 @@ static int socfpga_setup_ocram_self_refresh(void)
6767
if (!suspend_ocram_base) {
6868
pr_warn("%s: __arm_ioremap_exec failed!\n", __func__);
6969
ret = -ENOMEM;
70-
goto put_node;
70+
goto put_device;
7171
}
7272

7373
/* Copy the code that puts DDR in self refresh to ocram */
@@ -81,6 +81,8 @@ static int socfpga_setup_ocram_self_refresh(void)
8181
if (!socfpga_sdram_self_refresh_in_ocram)
8282
ret = -EFAULT;
8383

84+
put_device:
85+
put_device(&pdev->dev);
8486
put_node:
8587
of_node_put(np);
8688

‎arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -380,6 +380,7 @@
380380
reg = <0xffda4000 0x1000>;
381381
interrupts = <0 99 4>;
382382
resets = <&rst SPIM0_RESET>;
383+
reset-names = "spi";
383384
reg-io-width = <4>;
384385
num-cs = <4>;
385386
clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
@@ -393,6 +394,7 @@
393394
reg = <0xffda5000 0x1000>;
394395
interrupts = <0 100 4>;
395396
resets = <&rst SPIM1_RESET>;
397+
reset-names = "spi";
396398
reg-io-width = <4>;
397399
num-cs = <4>;
398400
clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;

‎arch/arm64/boot/dts/intel/socfpga_agilex.dtsi

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
/dts-v1/;
77
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
88
#include <dt-bindings/gpio/gpio.h>
9+
#include <dt-bindings/clock/agilex-clock.h>
910

1011
/ {
1112
compatible = "intel,socfpga-agilex";
@@ -101,6 +102,40 @@
101102
fpga-mgr = <&fpga_mgr>;
102103
};
103104

105+
clkmgr: clock-controller@ffd10000 {
106+
compatible = "intel,agilex-clkmgr";
107+
reg = <0xffd10000 0x1000>;
108+
#clock-cells = <1>;
109+
};
110+
111+
clocks {
112+
cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
113+
#clock-cells = <0>;
114+
compatible = "fixed-clock";
115+
};
116+
117+
cb_intosc_ls_clk: cb-intosc-ls-clk {
118+
#clock-cells = <0>;
119+
compatible = "fixed-clock";
120+
};
121+
122+
f2s_free_clk: f2s-free-clk {
123+
#clock-cells = <0>;
124+
compatible = "fixed-clock";
125+
};
126+
127+
osc1: osc1 {
128+
#clock-cells = <0>;
129+
compatible = "fixed-clock";
130+
};
131+
132+
qspi_clk: qspi-clk {
133+
#clock-cells = <0>;
134+
compatible = "fixed-clock";
135+
clock-frequency = <200000000>;
136+
};
137+
};
138+
104139
gmac0: ethernet@ff800000 {
105140
compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
106141
reg = <0xff800000 0x2000>;
@@ -114,6 +149,8 @@
114149
snps,multicast-filter-bins = <256>;
115150
iommus = <&smmu 1>;
116151
altr,sysmgr-syscon = <&sysmgr 0x44 0>;
152+
clocks = <&clkmgr AGILEX_EMAC0_CLK>;
153+
clock-names = "stmmaceth";
117154
status = "disabled";
118155
};
119156

@@ -130,6 +167,8 @@
130167
snps,multicast-filter-bins = <256>;
131168
iommus = <&smmu 2>;
132169
altr,sysmgr-syscon = <&sysmgr 0x48 8>;
170+
clocks = <&clkmgr AGILEX_EMAC1_CLK>;
171+
clock-names = "stmmaceth";
133172
status = "disabled";
134173
};
135174

@@ -146,6 +185,8 @@
146185
snps,multicast-filter-bins = <256>;
147186
iommus = <&smmu 3>;
148187
altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
188+
clocks = <&clkmgr AGILEX_EMAC2_CLK>;
189+
clock-names = "stmmaceth";
149190
status = "disabled";
150191
};
151192

@@ -196,6 +237,7 @@
196237
reg = <0xffc02800 0x100>;
197238
interrupts = <0 103 4>;
198239
resets = <&rst I2C0_RESET>;
240+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
199241
status = "disabled";
200242
};
201243

@@ -206,6 +248,7 @@
206248
reg = <0xffc02900 0x100>;
207249
interrupts = <0 104 4>;
208250
resets = <&rst I2C1_RESET>;
251+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
209252
status = "disabled";
210253
};
211254

@@ -216,6 +259,7 @@
216259
reg = <0xffc02a00 0x100>;
217260
interrupts = <0 105 4>;
218261
resets = <&rst I2C2_RESET>;
262+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
219263
status = "disabled";
220264
};
221265

@@ -226,6 +270,7 @@
226270
reg = <0xffc02b00 0x100>;
227271
interrupts = <0 106 4>;
228272
resets = <&rst I2C3_RESET>;
273+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
229274
status = "disabled";
230275
};
231276

@@ -236,6 +281,7 @@
236281
reg = <0xffc02c00 0x100>;
237282
interrupts = <0 107 4>;
238283
resets = <&rst I2C4_RESET>;
284+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
239285
status = "disabled";
240286
};
241287

@@ -248,6 +294,9 @@
248294
fifo-depth = <0x400>;
249295
resets = <&rst SDMMC_RESET>;
250296
reset-names = "reset";
297+
clocks = <&clkmgr AGILEX_L4_MP_CLK>,
298+
<&clkmgr AGILEX_SDMMC_CLK>;
299+
clock-names = "biu", "ciu";
251300
iommus = <&smmu 5>;
252301
status = "disabled";
253302
};
@@ -260,6 +309,10 @@
260309
<0xffb80000 0x1000>;
261310
reg-names = "nand_data", "denali_reg";
262311
interrupts = <0 97 4>;
312+
clocks = <&clkmgr AGILEX_NAND_CLK>,
313+
<&clkmgr AGILEX_NAND_X_CLK>,
314+
<&clkmgr AGILEX_NAND_ECC_CLK>;
315+
clock-names = "nand", "nand_x", "ecc";
263316
resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
264317
status = "disabled";
265318
};
@@ -286,6 +339,8 @@
286339
#dma-requests = <32>;
287340
resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
288341
reset-names = "dma", "dma-ocp";
342+
clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
343+
clock-names = "apb_pclk";
289344
};
290345

291346
rst: rstmgr@ffd11000 {
@@ -312,6 +367,9 @@
312367
<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
313368
<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
314369
stream-match-mask = <0x7ff0>;
370+
clocks = <&clkmgr AGILEX_MPU_CCU_CLK>,
371+
<&clkmgr AGILEX_L3_MAIN_FREE_CLK>,
372+
<&clkmgr AGILEX_L4_MAIN_CLK>;
315373
status = "disabled";
316374
};
317375

@@ -322,8 +380,10 @@
322380
reg = <0xffda4000 0x1000>;
323381
interrupts = <0 99 4>;
324382
resets = <&rst SPIM0_RESET>;
383+
reset-names = "spi";
325384
reg-io-width = <4>;
326385
num-cs = <4>;
386+
clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
327387
status = "disabled";
328388
};
329389

@@ -334,8 +394,10 @@
334394
reg = <0xffda5000 0x1000>;
335395
interrupts = <0 100 4>;
336396
resets = <&rst SPIM1_RESET>;
397+
reset-names = "spi";
337398
reg-io-width = <4>;
338399
num-cs = <4>;
400+
clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
339401
status = "disabled";
340402
};
341403

@@ -357,24 +419,32 @@
357419
compatible = "snps,dw-apb-timer";
358420
interrupts = <0 113 4>;
359421
reg = <0xffc03000 0x100>;
422+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
423+
clock-names = "timer";
360424
};
361425

362426
timer1: timer1@ffc03100 {
363427
compatible = "snps,dw-apb-timer";
364428
interrupts = <0 114 4>;
365429
reg = <0xffc03100 0x100>;
430+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
431+
clock-names = "timer";
366432
};
367433

368434
timer2: timer2@ffd00000 {
369435
compatible = "snps,dw-apb-timer";
370436
interrupts = <0 115 4>;
371437
reg = <0xffd00000 0x100>;
438+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
439+
clock-names = "timer";
372440
};
373441

374442
timer3: timer3@ffd00100 {
375443
compatible = "snps,dw-apb-timer";
376444
interrupts = <0 116 4>;
377445
reg = <0xffd00100 0x100>;
446+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
447+
clock-names = "timer";
378448
};
379449

380450
uart0: serial0@ffc02000 {
@@ -385,6 +455,7 @@
385455
reg-io-width = <4>;
386456
resets = <&rst UART0_RESET>;
387457
status = "disabled";
458+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
388459
};
389460

390461
uart1: serial1@ffc02100 {
@@ -394,6 +465,7 @@
394465
reg-shift = <2>;
395466
reg-io-width = <4>;
396467
resets = <&rst UART1_RESET>;
468+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
397469
status = "disabled";
398470
};
399471

@@ -411,6 +483,7 @@
411483
phy-names = "usb2-phy";
412484
resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
413485
reset-names = "dwc2", "dwc2-ecc";
486+
clocks = <&clkmgr AGILEX_USB_CLK>;
414487
iommus = <&smmu 6>;
415488
status = "disabled";
416489
};
@@ -424,6 +497,7 @@
424497
resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
425498
reset-names = "dwc2", "dwc2-ecc";
426499
iommus = <&smmu 7>;
500+
clocks = <&clkmgr AGILEX_USB_CLK>;
427501
status = "disabled";
428502
};
429503

@@ -432,6 +506,7 @@
432506
reg = <0xffd00200 0x100>;
433507
interrupts = <0 117 4>;
434508
resets = <&rst WATCHDOG0_RESET>;
509+
clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
435510
status = "disabled";
436511
};
437512

@@ -440,6 +515,7 @@
440515
reg = <0xffd00300 0x100>;
441516
interrupts = <0 118 4>;
442517
resets = <&rst WATCHDOG1_RESET>;
518+
clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
443519
status = "disabled";
444520
};
445521

@@ -448,6 +524,7 @@
448524
reg = <0xffd00400 0x100>;
449525
interrupts = <0 125 4>;
450526
resets = <&rst WATCHDOG2_RESET>;
527+
clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
451528
status = "disabled";
452529
};
453530

@@ -456,6 +533,7 @@
456533
reg = <0xffd00500 0x100>;
457534
interrupts = <0 126 4>;
458535
resets = <&rst WATCHDOG3_RESET>;
536+
clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
459537
status = "disabled";
460538
};
461539

@@ -533,6 +611,7 @@
533611
cdns,fifo-depth = <128>;
534612
cdns,fifo-width = <4>;
535613
cdns,trigger-address = <0x00000000>;
614+
clocks = <&qspi_clk>;
536615

537616
status = "disabled";
538617
};

‎arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,14 @@
4141
/* We expect the bootloader to fill in the reg */
4242
reg = <0 0 0 0>;
4343
};
44+
45+
soc {
46+
clocks {
47+
osc1 {
48+
clock-frequency = <25000000>;
49+
};
50+
};
51+
};
4452
};
4553

4654
&gpio1 {

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