Skip to content

Commit a09e3cf

Browse files
bebarinobebarino
committed
Merge branch 'clk-imx-old' into clk-imx
* clk-imx: (22 commits) clk: imx: composite-7ulp: Use NULL instead of 0 clk: imx: add missing MODULE_DESCRIPTION() macros clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate clk: imx: fracn-gppll: update rate table clk: imx: imx8qxp: Parent should be initialized earlier than the clock clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks clk: imx: imx8qxp: Add LVDS bypass clocks clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one clk: imx: imx8mn: add sai7_ipg_clk clock settings clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D clk: imx: imx8mp: fix clock tree update of TF-A managed clocks clk: imx: fracn-gppll: fix fractional part of PLL getting lost clk: imx: composite-7ulp: Check the PCC present bit clk: imx: composite-93: keep root clock on when mcore enabled clk: imx: composite-8m: Enable gate clk with mcore_booted clk: imx: imx6ul: fix default parent for enet*_ref_sel clk: imx: clk-audiomix: Correct parent clock for earc_phy and audpll clk: imx: clk-audiomix: Add CLK_SET_RATE_PARENT flags for clocks ...
2 parents 9395f3d + af05917 commit a09e3cf

File tree

15 files changed

+195
-50
lines changed

15 files changed

+195
-50
lines changed

‎Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,9 @@ properties:
4444
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h
4545
for the full list of i.MX8MP IMX8MP_CLK_AUDIOMIX_ clock IDs.
4646

47+
'#reset-cells':
48+
const: 1
49+
4750
required:
4851
- compatible
4952
- reg

‎drivers/clk/imx/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,7 @@ config CLK_IMX8MP
8181
tristate "IMX8MP CCM Clock Driver"
8282
depends on ARCH_MXC || COMPILE_TEST
8383
select MXC_CLK
84+
select AUXILIARY_BUS if RESET_CONTROLLER
8485
help
8586
Build the driver for i.MX8MP CCM Clock Driver
8687

‎drivers/clk/imx/clk-composite-7ulp.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
#include "../clk-fractional-divider.h"
1515
#include "clk.h"
1616

17+
#define PCG_PR_MASK BIT(31)
1718
#define PCG_PCS_SHIFT 24
1819
#define PCG_PCS_MASK 0x7
1920
#define PCG_CGC_SHIFT 30
@@ -78,6 +79,12 @@ static struct clk_hw *imx_ulp_clk_hw_composite(const char *name,
7879
struct clk_hw *hw;
7980
u32 val;
8081

82+
val = readl(reg);
83+
if (!(val & PCG_PR_MASK)) {
84+
pr_info("PCC PR is 0 for clk:%s, bypass\n", name);
85+
return NULL;
86+
}
87+
8188
if (mux_present) {
8289
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
8390
if (!mux)

‎drivers/clk/imx/clk-composite-8m.c

Lines changed: 42 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -204,6 +204,34 @@ static const struct clk_ops imx8m_clk_composite_mux_ops = {
204204
.determine_rate = imx8m_clk_composite_mux_determine_rate,
205205
};
206206

207+
static int imx8m_clk_composite_gate_enable(struct clk_hw *hw)
208+
{
209+
struct clk_gate *gate = to_clk_gate(hw);
210+
unsigned long flags;
211+
u32 val;
212+
213+
spin_lock_irqsave(gate->lock, flags);
214+
215+
val = readl(gate->reg);
216+
val |= BIT(gate->bit_idx);
217+
writel(val, gate->reg);
218+
219+
spin_unlock_irqrestore(gate->lock, flags);
220+
221+
return 0;
222+
}
223+
224+
static void imx8m_clk_composite_gate_disable(struct clk_hw *hw)
225+
{
226+
/* composite clk requires the disable hook */
227+
}
228+
229+
static const struct clk_ops imx8m_clk_composite_gate_ops = {
230+
.enable = imx8m_clk_composite_gate_enable,
231+
.disable = imx8m_clk_composite_gate_disable,
232+
.is_enabled = clk_gate_is_enabled,
233+
};
234+
207235
struct clk_hw *__imx8m_clk_hw_composite(const char *name,
208236
const char * const *parent_names,
209237
int num_parents, void __iomem *reg,
@@ -217,6 +245,7 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
217245
struct clk_mux *mux;
218246
const struct clk_ops *divider_ops;
219247
const struct clk_ops *mux_ops;
248+
const struct clk_ops *gate_ops;
220249

221250
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
222251
if (!mux)
@@ -257,20 +286,22 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
257286
div->flags = CLK_DIVIDER_ROUND_CLOSEST;
258287

259288
/* skip registering the gate ops if M4 is enabled */
260-
if (!mcore_booted) {
261-
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
262-
if (!gate)
263-
goto free_div;
264-
265-
gate_hw = &gate->hw;
266-
gate->reg = reg;
267-
gate->bit_idx = PCG_CGC_SHIFT;
268-
gate->lock = &imx_ccm_lock;
269-
}
289+
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
290+
if (!gate)
291+
goto free_div;
292+
293+
gate_hw = &gate->hw;
294+
gate->reg = reg;
295+
gate->bit_idx = PCG_CGC_SHIFT;
296+
gate->lock = &imx_ccm_lock;
297+
if (!mcore_booted)
298+
gate_ops = &clk_gate_ops;
299+
else
300+
gate_ops = &imx8m_clk_composite_gate_ops;
270301

271302
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
272303
mux_hw, mux_ops, div_hw,
273-
divider_ops, gate_hw, &clk_gate_ops, flags);
304+
divider_ops, gate_hw, gate_ops, flags);
274305
if (IS_ERR(hw))
275306
goto free_gate;
276307

‎drivers/clk/imx/clk-composite-93.c

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,13 @@ static int imx93_clk_composite_gate_enable(struct clk_hw *hw)
7676

7777
static void imx93_clk_composite_gate_disable(struct clk_hw *hw)
7878
{
79+
/*
80+
* Skip disable the root clock gate if mcore enabled.
81+
* The root clock may be used by the mcore.
82+
*/
83+
if (mcore_booted)
84+
return;
85+
7986
imx93_clk_composite_gate_endisable(hw, 0);
8087
}
8188

@@ -222,7 +229,7 @@ struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *p
222229
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
223230
mux_hw, &clk_mux_ro_ops, div_hw,
224231
&clk_divider_ro_ops, NULL, NULL, flags);
225-
} else if (!mcore_booted) {
232+
} else {
226233
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
227234
if (!gate)
228235
goto fail;
@@ -238,12 +245,6 @@ struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *p
238245
&imx93_clk_composite_divider_ops, gate_hw,
239246
&imx93_clk_composite_gate_ops,
240247
flags | CLK_SET_RATE_NO_REPARENT);
241-
} else {
242-
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
243-
mux_hw, &imx93_clk_composite_mux_ops, div_hw,
244-
&imx93_clk_composite_divider_ops, NULL,
245-
&imx93_clk_composite_gate_ops,
246-
flags | CLK_SET_RATE_NO_REPARENT);
247248
}
248249

249250
if (IS_ERR(hw))

‎drivers/clk/imx/clk-fracn-gppll.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,7 @@ struct clk_fracn_gppll {
7878
* The Fvco should be in range 2.5Ghz to 5Ghz
7979
*/
8080
static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
81+
PLL_FRACN_GP(1039500000U, 173, 25, 100, 1, 4),
8182
PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
8283
PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
8384
PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
@@ -106,6 +107,7 @@ static const struct imx_fracn_gppll_rate_table int_tbl[] = {
106107
PLL_FRACN_GP_INTEGER(1700000000U, 141, 1, 2),
107108
PLL_FRACN_GP_INTEGER(1400000000U, 175, 1, 3),
108109
PLL_FRACN_GP_INTEGER(900000000U, 150, 1, 4),
110+
PLL_FRACN_GP_INTEGER(800000000U, 200, 1, 6),
109111
};
110112

111113
struct imx_fracn_gppll_clk imx_fracn_gppll_integer = {
@@ -291,6 +293,10 @@ static int clk_fracn_gppll_prepare(struct clk_hw *hw)
291293
if (val & POWERUP_MASK)
292294
return 0;
293295

296+
if (pll->flags & CLK_FRACN_GPPLL_FRACN)
297+
writel_relaxed(readl_relaxed(pll->base + PLL_NUMERATOR),
298+
pll->base + PLL_NUMERATOR);
299+
294300
val |= CLKMUX_BYPASS;
295301
writel_relaxed(val, pll->base + PLL_CTRL);
296302

‎drivers/clk/imx/clk-imx7d.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -498,14 +498,14 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
498498
hws[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_hw_mux2_flags("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel), CLK_SET_PARENT_GATE);
499499
hws[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_hw_mux2_flags("nand_usdhc_src", base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel), CLK_SET_PARENT_GATE);
500500
hws[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_phym_src", base + 0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel), CLK_SET_PARENT_GATE);
501-
hws[IMX7D_DRAM_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel), CLK_SET_PARENT_GATE);
501+
hws[IMX7D_DRAM_ROOT_SRC] = imx_clk_hw_mux2("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel));
502502
hws[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_phym_alt_src", base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel), CLK_SET_PARENT_GATE);
503-
hws[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel), CLK_SET_PARENT_GATE);
503+
hws[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_hw_mux2("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel));
504504
hws[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_hw_mux2_flags("usb_hsic_src", base + 0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel), CLK_SET_PARENT_GATE);
505505
hws[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel), CLK_SET_PARENT_GATE);
506506
hws[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel), CLK_SET_PARENT_GATE);
507507
hws[IMX7D_EPDC_PIXEL_ROOT_SRC] = imx_clk_hw_mux2_flags("epdc_pixel_src", base + 0xa280, 24, 3, epdc_pixel_sel, ARRAY_SIZE(epdc_pixel_sel), CLK_SET_PARENT_GATE);
508-
hws[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_hw_mux2_flags("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel), CLK_SET_PARENT_GATE);
508+
hws[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_hw_mux2_flags("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel), CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT);
509509
hws[IMX7D_MIPI_DSI_ROOT_SRC] = imx_clk_hw_mux2_flags("mipi_dsi_src", base + 0xa380, 24, 3, mipi_dsi_sel, ARRAY_SIZE(mipi_dsi_sel), CLK_SET_PARENT_GATE);
510510
hws[IMX7D_MIPI_CSI_ROOT_SRC] = imx_clk_hw_mux2_flags("mipi_csi_src", base + 0xa400, 24, 3, mipi_csi_sel, ARRAY_SIZE(mipi_csi_sel), CLK_SET_PARENT_GATE);
511511
hws[IMX7D_MIPI_DPHY_ROOT_SRC] = imx_clk_hw_mux2_flags("mipi_dphy_src", base + 0xa480, 24, 3, mipi_dphy_sel, ARRAY_SIZE(mipi_dphy_sel), CLK_SET_PARENT_GATE);

‎drivers/clk/imx/clk-imx8mm.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -432,7 +432,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
432432
/* BUS */
433433
hws[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi", imx8mm_main_axi_sels, base + 0x8800);
434434
hws[IMX8MM_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mm_enet_axi_sels, base + 0x8880);
435-
hws[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus_critical("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900);
435+
hws[IMX8MM_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900);
436436
hws[IMX8MM_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mm_vpu_bus_sels, base + 0x8980);
437437
hws[IMX8MM_CLK_DISP_AXI] = imx8m_clk_hw_composite_bus("disp_axi", imx8mm_disp_axi_sels, base + 0x8a00);
438438
hws[IMX8MM_CLK_DISP_APB] = imx8m_clk_hw_composite_bus("disp_apb", imx8mm_disp_apb_sels, base + 0x8a80);

‎drivers/clk/imx/clk-imx8mn.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -583,6 +583,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
583583
hws[IMX8MN_CLK_SDMA2_ROOT] = imx_clk_hw_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0);
584584
hws[IMX8MN_CLK_SDMA3_ROOT] = imx_clk_hw_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0);
585585
hws[IMX8MN_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root_clk", "sai7", base + 0x4650, 0, &share_count_sai7);
586+
hws[IMX8MN_CLK_SAI7_IPG] = imx_clk_hw_gate2_shared2("sai7_ipg_clk", "ipg_audio_root", base + 0x4650, 0, &share_count_sai7);
586587

587588
hws[IMX8MN_CLK_GPT_3M] = imx_clk_hw_fixed_factor("gpt_3m", "osc_24m", 1, 8);
588589

‎drivers/clk/imx/clk-imx8mp-audiomix.c

Lines changed: 80 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@
55
* Copyright (C) 2022 Marek Vasut <[email protected]>
66
*/
77

8+
#include <linux/auxiliary_bus.h>
89
#include <linux/clk-provider.h>
910
#include <linux/device.h>
1011
#include <linux/io.h>
@@ -13,6 +14,7 @@
1314
#include <linux/of.h>
1415
#include <linux/platform_device.h>
1516
#include <linux/pm_runtime.h>
17+
#include <linux/slab.h>
1618

1719
#include <dt-bindings/clock/imx8mp-clock.h>
1820

@@ -154,6 +156,15 @@ static const struct clk_parent_data clk_imx8mp_audiomix_pll_bypass_sels[] = {
154156
PDM_SEL, 2, 0 \
155157
}
156158

159+
#define CLK_GATE_PARENT(gname, cname, pname) \
160+
{ \
161+
gname"_cg", \
162+
IMX8MP_CLK_AUDIOMIX_##cname, \
163+
{ .fw_name = pname, .name = pname }, NULL, 1, \
164+
CLKEN0 + 4 * !!(IMX8MP_CLK_AUDIOMIX_##cname / 32), \
165+
1, IMX8MP_CLK_AUDIOMIX_##cname % 32 \
166+
}
167+
157168
struct clk_imx8mp_audiomix_sel {
158169
const char *name;
159170
int clkid;
@@ -171,14 +182,14 @@ static struct clk_imx8mp_audiomix_sel sels[] = {
171182
CLK_GATE("earc", EARC_IPG),
172183
CLK_GATE("ocrama", OCRAMA_IPG),
173184
CLK_GATE("aud2htx", AUD2HTX_IPG),
174-
CLK_GATE("earc_phy", EARC_PHY),
185+
CLK_GATE_PARENT("earc_phy", EARC_PHY, "sai_pll_out_div2"),
175186
CLK_GATE("sdma2", SDMA2_ROOT),
176187
CLK_GATE("sdma3", SDMA3_ROOT),
177188
CLK_GATE("spba2", SPBA2_ROOT),
178189
CLK_GATE("dsp", DSP_ROOT),
179190
CLK_GATE("dspdbg", DSPDBG_ROOT),
180191
CLK_GATE("edma", EDMA_ROOT),
181-
CLK_GATE("audpll", AUDPLL_ROOT),
192+
CLK_GATE_PARENT("audpll", AUDPLL_ROOT, "osc_24m"),
182193
CLK_GATE("mu2", MU2_ROOT),
183194
CLK_GATE("mu3", MU3_ROOT),
184195
CLK_PDM,
@@ -217,6 +228,63 @@ struct clk_imx8mp_audiomix_priv {
217228
struct clk_hw_onecell_data clk_data;
218229
};
219230

231+
#if IS_ENABLED(CONFIG_RESET_CONTROLLER)
232+
233+
static void clk_imx8mp_audiomix_reset_unregister_adev(void *_adev)
234+
{
235+
struct auxiliary_device *adev = _adev;
236+
237+
auxiliary_device_delete(adev);
238+
auxiliary_device_uninit(adev);
239+
}
240+
241+
static void clk_imx8mp_audiomix_reset_adev_release(struct device *dev)
242+
{
243+
struct auxiliary_device *adev = to_auxiliary_dev(dev);
244+
245+
kfree(adev);
246+
}
247+
248+
static int clk_imx8mp_audiomix_reset_controller_register(struct device *dev,
249+
struct clk_imx8mp_audiomix_priv *priv)
250+
{
251+
struct auxiliary_device *adev __free(kfree) = NULL;
252+
int ret;
253+
254+
if (!of_property_present(dev->of_node, "#reset-cells"))
255+
return 0;
256+
257+
adev = kzalloc(sizeof(*adev), GFP_KERNEL);
258+
if (!adev)
259+
return -ENOMEM;
260+
261+
adev->name = "reset";
262+
adev->dev.parent = dev;
263+
adev->dev.release = clk_imx8mp_audiomix_reset_adev_release;
264+
265+
ret = auxiliary_device_init(adev);
266+
if (ret)
267+
return ret;
268+
269+
ret = auxiliary_device_add(adev);
270+
if (ret) {
271+
auxiliary_device_uninit(adev);
272+
return ret;
273+
}
274+
275+
return devm_add_action_or_reset(dev, clk_imx8mp_audiomix_reset_unregister_adev,
276+
no_free_ptr(adev));
277+
}
278+
279+
#else /* !CONFIG_RESET_CONTROLLER */
280+
281+
static int clk_imx8mp_audiomix_reset_controller_register(struct clk_imx8mp_audiomix_priv *priv)
282+
{
283+
return 0;
284+
}
285+
286+
#endif /* !CONFIG_RESET_CONTROLLER */
287+
220288
static void clk_imx8mp_audiomix_save_restore(struct device *dev, bool save)
221289
{
222290
struct clk_imx8mp_audiomix_priv *priv = dev_get_drvdata(dev);
@@ -269,12 +337,12 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
269337
for (i = 0; i < ARRAY_SIZE(sels); i++) {
270338
if (sels[i].num_parents == 1) {
271339
hw = devm_clk_hw_register_gate_parent_data(dev,
272-
sels[i].name, &sels[i].parent, 0,
340+
sels[i].name, &sels[i].parent, CLK_SET_RATE_PARENT,
273341
base + sels[i].reg, sels[i].shift, 0, NULL);
274342
} else {
275343
hw = devm_clk_hw_register_mux_parent_data_table(dev,
276344
sels[i].name, sels[i].parents,
277-
sels[i].num_parents, 0,
345+
sels[i].num_parents, CLK_SET_RATE_PARENT,
278346
base + sels[i].reg,
279347
sels[i].shift, sels[i].width,
280348
0, NULL, NULL);
@@ -317,7 +385,8 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
317385
clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = hw;
318386

319387
hw = devm_clk_hw_register_gate(dev, "sai_pll_out", "sai_pll_bypass",
320-
0, base + SAI_PLL_GNRL_CTL, 13,
388+
CLK_SET_RATE_PARENT,
389+
base + SAI_PLL_GNRL_CTL, 13,
321390
0, NULL);
322391
if (IS_ERR(hw)) {
323392
ret = PTR_ERR(hw);
@@ -326,7 +395,8 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
326395
clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = hw;
327396

328397
hw = devm_clk_hw_register_fixed_factor(dev, "sai_pll_out_div2",
329-
"sai_pll_out", 0, 1, 2);
398+
"sai_pll_out",
399+
CLK_SET_RATE_PARENT, 1, 2);
330400
if (IS_ERR(hw)) {
331401
ret = PTR_ERR(hw);
332402
goto err_clk_register;
@@ -337,6 +407,10 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
337407
if (ret)
338408
goto err_clk_register;
339409

410+
ret = clk_imx8mp_audiomix_reset_controller_register(dev, priv);
411+
if (ret)
412+
goto err_clk_register;
413+
340414
pm_runtime_put_sync(dev);
341415
return 0;
342416

0 commit comments

Comments
 (0)