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Merge tag 'amd-drm-next-6.8-2023-12-08' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-6.8-2023-12-08: amdgpu: - SR-IOV fixes - DCN 3.5 updates - Backlight fixes - MST fixes - DMCUB fixes - DPIA fixes - Display powergating updates - Enable writeback connectors - Misc code cleanups - Add more register state debugging for aquavanjaram - Suspend fix - Clockgating fixes - SMU 14 updates - PSR fixes - MES logging updates - Misc fixes amdkfd: - SVM fix radeon: - Fix potential memory leaks in error paths Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 6734cd0 + 47c4533 commit a0a2895

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+2112
-424
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2147,6 +2147,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
21472147
amdgpu_debugfs_firmware_init(adev);
21482148
amdgpu_ta_if_debugfs_init(adev);
21492149

2150+
amdgpu_debugfs_mes_event_log_init(adev);
2151+
21502152
#if defined(CONFIG_DRM_AMD_DC)
21512153
if (adev->dc_enabled)
21522154
dtn_debugfs_init(adev);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,3 +32,5 @@ void amdgpu_debugfs_fini(struct amdgpu_device *adev);
3232
void amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
3333
void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
3434
void amdgpu_debugfs_gem_init(struct amdgpu_device *adev);
35+
void amdgpu_debugfs_mes_event_log_init(struct amdgpu_device *adev);
36+

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,26 @@ static int amdgpu_mes_doorbell_init(struct amdgpu_device *adev)
9898
return 0;
9999
}
100100

101+
static int amdgpu_mes_event_log_init(struct amdgpu_device *adev)
102+
{
103+
int r;
104+
105+
r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
106+
AMDGPU_GEM_DOMAIN_GTT,
107+
&adev->mes.event_log_gpu_obj,
108+
&adev->mes.event_log_gpu_addr,
109+
&adev->mes.event_log_cpu_addr);
110+
if (r) {
111+
dev_warn(adev->dev, "failed to create MES event log buffer (%d)", r);
112+
return r;
113+
}
114+
115+
memset(adev->mes.event_log_cpu_addr, 0, PAGE_SIZE);
116+
117+
return 0;
118+
119+
}
120+
101121
static void amdgpu_mes_doorbell_free(struct amdgpu_device *adev)
102122
{
103123
bitmap_free(adev->mes.doorbell_bitmap);
@@ -182,8 +202,14 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
182202
if (r)
183203
goto error;
184204

205+
r = amdgpu_mes_event_log_init(adev);
206+
if (r)
207+
goto error_doorbell;
208+
185209
return 0;
186210

211+
error_doorbell:
212+
amdgpu_mes_doorbell_free(adev);
187213
error:
188214
amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
189215
amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
@@ -199,6 +225,10 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
199225

200226
void amdgpu_mes_fini(struct amdgpu_device *adev)
201227
{
228+
amdgpu_bo_free_kernel(&adev->mes.event_log_gpu_obj,
229+
&adev->mes.event_log_gpu_addr,
230+
&adev->mes.event_log_cpu_addr);
231+
202232
amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
203233
amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
204234
amdgpu_device_wb_free(adev, adev->mes.read_val_offs);
@@ -1479,3 +1509,34 @@ int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe)
14791509
amdgpu_ucode_release(&adev->mes.fw[pipe]);
14801510
return r;
14811511
}
1512+
1513+
#if defined(CONFIG_DEBUG_FS)
1514+
1515+
static int amdgpu_debugfs_mes_event_log_show(struct seq_file *m, void *unused)
1516+
{
1517+
struct amdgpu_device *adev = m->private;
1518+
uint32_t *mem = (uint32_t *)(adev->mes.event_log_cpu_addr);
1519+
1520+
seq_hex_dump(m, "", DUMP_PREFIX_OFFSET, 32, 4,
1521+
mem, PAGE_SIZE, false);
1522+
1523+
return 0;
1524+
}
1525+
1526+
1527+
DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_mes_event_log);
1528+
1529+
#endif
1530+
1531+
void amdgpu_debugfs_mes_event_log_init(struct amdgpu_device *adev)
1532+
{
1533+
1534+
#if defined(CONFIG_DEBUG_FS)
1535+
struct drm_minor *minor = adev_to_drm(adev)->primary;
1536+
struct dentry *root = minor->debugfs_root;
1537+
1538+
debugfs_create_file("amdgpu_mes_event_log", 0444, root,
1539+
adev, &amdgpu_debugfs_mes_event_log_fops);
1540+
1541+
#endif
1542+
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -133,6 +133,11 @@ struct amdgpu_mes {
133133
uint32_t num_mes_dbs;
134134
unsigned long *doorbell_bitmap;
135135

136+
/* MES event log buffer */
137+
struct amdgpu_bo *event_log_gpu_obj;
138+
uint64_t event_log_gpu_addr;
139+
void *event_log_cpu_addr;
140+
136141
/* ip specific functions */
137142
const struct amdgpu_mes_funcs *funcs;
138143
};

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -416,6 +416,10 @@ struct amdgpu_crtc {
416416

417417
int otg_inst;
418418
struct drm_pending_vblank_event *event;
419+
420+
bool wb_pending;
421+
bool wb_enabled;
422+
struct drm_writeback_connector *wb_conn;
419423
};
420424

421425
struct amdgpu_encoder_atom_dig {

‎drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c

Lines changed: 203 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -848,6 +848,198 @@ static ssize_t aqua_vanjaram_read_xgmi_state(struct amdgpu_device *adev,
848848
return xgmi_reg_state->common_header.structure_size;
849849
}
850850

851+
#define smnreg_0x11C00070 0x11C00070
852+
#define smnreg_0x11C00210 0x11C00210
853+
854+
static struct aqua_reg_list wafl_reg_addrs[] = {
855+
{ smnreg_0x11C00070, 4, DW_ADDR_INCR },
856+
{ smnreg_0x11C00210, 1, 0 },
857+
};
858+
859+
#define WAFL_LINK_REG(smnreg, l) ((smnreg) | (l << 20))
860+
861+
#define NUM_WAFL_SMN_REGS 5
862+
863+
static ssize_t aqua_vanjaram_read_wafl_state(struct amdgpu_device *adev,
864+
void *buf, size_t max_size)
865+
{
866+
struct amdgpu_reg_state_wafl_v1_0 *wafl_reg_state;
867+
uint32_t start_addr, incrx, num_regs, szbuf;
868+
struct amdgpu_regs_wafl_v1_0 *wafl_regs;
869+
struct amdgpu_smn_reg_data *reg_data;
870+
const int max_wafl_instances = 8;
871+
int inst = 0, i, j, r, n;
872+
const int wafl_inst = 2;
873+
void *p;
874+
875+
if (!buf || !max_size)
876+
return -EINVAL;
877+
878+
wafl_reg_state = (struct amdgpu_reg_state_wafl_v1_0 *)buf;
879+
880+
szbuf = sizeof(*wafl_reg_state) +
881+
amdgpu_reginst_size(max_wafl_instances, sizeof(*wafl_regs),
882+
NUM_WAFL_SMN_REGS);
883+
884+
if (max_size < szbuf)
885+
return -EOVERFLOW;
886+
887+
p = &wafl_reg_state->wafl_state_regs[0];
888+
for_each_inst(i, adev->aid_mask) {
889+
for (j = 0; j < wafl_inst; ++j) {
890+
wafl_regs = (struct amdgpu_regs_wafl_v1_0 *)p;
891+
wafl_regs->inst_header.instance = inst++;
892+
893+
wafl_regs->inst_header.state = AMDGPU_INST_S_OK;
894+
wafl_regs->inst_header.num_smn_regs = NUM_WAFL_SMN_REGS;
895+
896+
reg_data = wafl_regs->smn_reg_values;
897+
898+
for (r = 0; r < ARRAY_SIZE(wafl_reg_addrs); r++) {
899+
start_addr = wafl_reg_addrs[r].start_addr;
900+
incrx = wafl_reg_addrs[r].incrx;
901+
num_regs = wafl_reg_addrs[r].num_regs;
902+
for (n = 0; n < num_regs; n++) {
903+
aqua_read_smn_ext(
904+
adev, reg_data,
905+
WAFL_LINK_REG(start_addr, j) +
906+
n * incrx,
907+
i);
908+
++reg_data;
909+
}
910+
}
911+
p = reg_data;
912+
}
913+
}
914+
915+
wafl_reg_state->common_header.structure_size = szbuf;
916+
wafl_reg_state->common_header.format_revision = 1;
917+
wafl_reg_state->common_header.content_revision = 0;
918+
wafl_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_WAFL;
919+
wafl_reg_state->common_header.num_instances = max_wafl_instances;
920+
921+
return wafl_reg_state->common_header.structure_size;
922+
}
923+
924+
#define smnreg_0x1B311060 0x1B311060
925+
#define smnreg_0x1B411060 0x1B411060
926+
#define smnreg_0x1B511060 0x1B511060
927+
#define smnreg_0x1B611060 0x1B611060
928+
929+
#define smnreg_0x1C307120 0x1C307120
930+
#define smnreg_0x1C317120 0x1C317120
931+
932+
#define smnreg_0x1C320830 0x1C320830
933+
#define smnreg_0x1C380830 0x1C380830
934+
#define smnreg_0x1C3D0830 0x1C3D0830
935+
#define smnreg_0x1C420830 0x1C420830
936+
937+
#define smnreg_0x1C320100 0x1C320100
938+
#define smnreg_0x1C380100 0x1C380100
939+
#define smnreg_0x1C3D0100 0x1C3D0100
940+
#define smnreg_0x1C420100 0x1C420100
941+
942+
#define smnreg_0x1B310500 0x1B310500
943+
#define smnreg_0x1C300400 0x1C300400
944+
945+
#define USR_CAKE_INCR 0x11000
946+
#define USR_LINK_INCR 0x100000
947+
#define USR_CP_INCR 0x10000
948+
949+
#define NUM_USR_SMN_REGS 20
950+
951+
struct aqua_reg_list usr_reg_addrs[] = {
952+
{ smnreg_0x1B311060, 4, DW_ADDR_INCR },
953+
{ smnreg_0x1B411060, 4, DW_ADDR_INCR },
954+
{ smnreg_0x1B511060, 4, DW_ADDR_INCR },
955+
{ smnreg_0x1B611060, 4, DW_ADDR_INCR },
956+
{ smnreg_0x1C307120, 2, DW_ADDR_INCR },
957+
{ smnreg_0x1C317120, 2, DW_ADDR_INCR },
958+
};
959+
960+
#define NUM_USR1_SMN_REGS 46
961+
struct aqua_reg_list usr1_reg_addrs[] = {
962+
{ smnreg_0x1C320830, 6, USR_CAKE_INCR },
963+
{ smnreg_0x1C380830, 5, USR_CAKE_INCR },
964+
{ smnreg_0x1C3D0830, 5, USR_CAKE_INCR },
965+
{ smnreg_0x1C420830, 4, USR_CAKE_INCR },
966+
{ smnreg_0x1C320100, 6, USR_CAKE_INCR },
967+
{ smnreg_0x1C380100, 5, USR_CAKE_INCR },
968+
{ smnreg_0x1C3D0100, 5, USR_CAKE_INCR },
969+
{ smnreg_0x1C420100, 4, USR_CAKE_INCR },
970+
{ smnreg_0x1B310500, 4, USR_LINK_INCR },
971+
{ smnreg_0x1C300400, 2, USR_CP_INCR },
972+
};
973+
974+
static ssize_t aqua_vanjaram_read_usr_state(struct amdgpu_device *adev,
975+
void *buf, size_t max_size,
976+
int reg_state)
977+
{
978+
uint32_t start_addr, incrx, num_regs, szbuf, num_smn;
979+
struct amdgpu_reg_state_usr_v1_0 *usr_reg_state;
980+
struct amdgpu_regs_usr_v1_0 *usr_regs;
981+
struct amdgpu_smn_reg_data *reg_data;
982+
const int max_usr_instances = 4;
983+
struct aqua_reg_list *reg_addrs;
984+
int inst = 0, i, n, r, arr_size;
985+
void *p;
986+
987+
if (!buf || !max_size)
988+
return -EINVAL;
989+
990+
switch (reg_state) {
991+
case AMDGPU_REG_STATE_TYPE_USR:
992+
arr_size = ARRAY_SIZE(usr_reg_addrs);
993+
reg_addrs = usr_reg_addrs;
994+
num_smn = NUM_USR_SMN_REGS;
995+
break;
996+
case AMDGPU_REG_STATE_TYPE_USR_1:
997+
arr_size = ARRAY_SIZE(usr1_reg_addrs);
998+
reg_addrs = usr1_reg_addrs;
999+
num_smn = NUM_USR1_SMN_REGS;
1000+
break;
1001+
default:
1002+
return -EINVAL;
1003+
}
1004+
1005+
usr_reg_state = (struct amdgpu_reg_state_usr_v1_0 *)buf;
1006+
1007+
szbuf = sizeof(*usr_reg_state) + amdgpu_reginst_size(max_usr_instances,
1008+
sizeof(*usr_regs),
1009+
num_smn);
1010+
if (max_size < szbuf)
1011+
return -EOVERFLOW;
1012+
1013+
p = &usr_reg_state->usr_state_regs[0];
1014+
for_each_inst(i, adev->aid_mask) {
1015+
usr_regs = (struct amdgpu_regs_usr_v1_0 *)p;
1016+
usr_regs->inst_header.instance = inst++;
1017+
usr_regs->inst_header.state = AMDGPU_INST_S_OK;
1018+
usr_regs->inst_header.num_smn_regs = num_smn;
1019+
reg_data = usr_regs->smn_reg_values;
1020+
1021+
for (r = 0; r < arr_size; r++) {
1022+
start_addr = reg_addrs[r].start_addr;
1023+
incrx = reg_addrs[r].incrx;
1024+
num_regs = reg_addrs[r].num_regs;
1025+
for (n = 0; n < num_regs; n++) {
1026+
aqua_read_smn_ext(adev, reg_data,
1027+
start_addr + n * incrx, i);
1028+
reg_data++;
1029+
}
1030+
}
1031+
p = reg_data;
1032+
}
1033+
1034+
usr_reg_state->common_header.structure_size = szbuf;
1035+
usr_reg_state->common_header.format_revision = 1;
1036+
usr_reg_state->common_header.content_revision = 0;
1037+
usr_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_USR;
1038+
usr_reg_state->common_header.num_instances = max_usr_instances;
1039+
1040+
return usr_reg_state->common_header.structure_size;
1041+
}
1042+
8511043
ssize_t aqua_vanjaram_get_reg_state(struct amdgpu_device *adev,
8521044
enum amdgpu_reg_state reg_state, void *buf,
8531045
size_t max_size)
@@ -861,6 +1053,17 @@ ssize_t aqua_vanjaram_get_reg_state(struct amdgpu_device *adev,
8611053
case AMDGPU_REG_STATE_TYPE_XGMI:
8621054
size = aqua_vanjaram_read_xgmi_state(adev, buf, max_size);
8631055
break;
1056+
case AMDGPU_REG_STATE_TYPE_WAFL:
1057+
size = aqua_vanjaram_read_wafl_state(adev, buf, max_size);
1058+
break;
1059+
case AMDGPU_REG_STATE_TYPE_USR:
1060+
size = aqua_vanjaram_read_usr_state(adev, buf, max_size,
1061+
AMDGPU_REG_STATE_TYPE_USR);
1062+
break;
1063+
case AMDGPU_REG_STATE_TYPE_USR_1:
1064+
size = aqua_vanjaram_read_usr_state(
1065+
adev, buf, max_size, AMDGPU_REG_STATE_TYPE_USR_1);
1066+
break;
8641067
default:
8651068
return -EINVAL;
8661069
}

‎drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -408,6 +408,8 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
408408
mes_set_hw_res_pkt.enable_reg_active_poll = 1;
409409
mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;
410410
mes_set_hw_res_pkt.oversubscription_timer = 50;
411+
mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
412+
mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr;
411413

412414
return mes_v11_0_submit_pkt_and_poll_completion(mes,
413415
&mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),

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