@@ -252,11 +252,12 @@ static void rz_mtu3_start_stop_ch(struct rz_mtu3_channel *ch, bool start)
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u16 offset ;
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u8 bitpos ;
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+ offset = rz_mtu3_get_tstr_offset (ch );
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+ bitpos = rz_mtu3_get_tstr_bit_pos (ch );
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+
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/* start stop register shared by multiple timer channels */
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raw_spin_lock_irqsave (& priv -> lock , flags );
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- offset = rz_mtu3_get_tstr_offset (ch );
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- bitpos = rz_mtu3_get_tstr_bit_pos (ch );
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tstr = rz_mtu3_shared_reg_read (ch , offset );
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__assign_bit (bitpos , & tstr , start );
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rz_mtu3_shared_reg_write (ch , offset , tstr );
@@ -269,21 +270,18 @@ bool rz_mtu3_is_enabled(struct rz_mtu3_channel *ch)
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struct rz_mtu3 * mtu = dev_get_drvdata (ch -> dev -> parent );
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struct rz_mtu3_priv * priv = mtu -> priv_data ;
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unsigned long flags , tstr ;
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- bool ret = false;
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u16 offset ;
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u8 bitpos ;
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- /* start stop register shared by multiple timer channels */
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- raw_spin_lock_irqsave (& priv -> lock , flags );
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-
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offset = rz_mtu3_get_tstr_offset (ch );
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bitpos = rz_mtu3_get_tstr_bit_pos (ch );
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- tstr = rz_mtu3_shared_reg_read (ch , offset );
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- ret = tstr & BIT (bitpos );
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+ /* start stop register shared by multiple timer channels */
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+ raw_spin_lock_irqsave (& priv -> lock , flags );
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+ tstr = rz_mtu3_shared_reg_read (ch , offset );
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raw_spin_unlock_irqrestore (& priv -> lock , flags );
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- return ret ;
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+ return tstr & BIT ( bitpos ) ;
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}
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EXPORT_SYMBOL_GPL (rz_mtu3_is_enabled );
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