drm/nouveau/disp/gm200-: fix NV_PDISP_SOR_HDMI2_CTRL(n) selection

Ben Skeggs · Ben Skeggs · commit a1ef8bad506e · 2020-06-01T17:28:41.000+10:00
This is a SOR register, and not indexed by the bound head.

Fixes display not coming up on high-bandwidth HDMI displays under a
number of configurations.

Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c
@@ -27,10 +27,10 @@ void
 gm200_hdmi_scdc(struct nvkm_ior *ior, int head, u8 scdc)
 {
 	struct nvkm_device *device = ior->disp->engine.subdev.device;
-	const u32 hoff = head * 0x800;
+	const u32 soff = nv50_ior_base(ior);
 	const u32 ctrl = scdc & 0x3;
 
-	nvkm_mask(device, 0x61c5bc + hoff, 0x00000003, ctrl);
+	nvkm_mask(device, 0x61c5bc + soff, 0x00000003, ctrl);
 
 	ior->tmds.high_speed = !!(scdc & 0x2);
 }

Original file line number	Diff line number	Diff line change
`@@ -27,10 +27,10 @@ void`
`27`	`27`	`gm200_hdmi_scdc(struct nvkm_ior *ior, int head, u8 scdc)`
`28`	`28`	`{`
`29`	`29`	`struct nvkm_device *device = ior->disp->engine.subdev.device;`
`30`		`- const u32 hoff = head * 0x800;`
	`30`	`+ const u32 soff = nv50_ior_base(ior);`
`31`	`31`	`const u32 ctrl = scdc & 0x3;`
`32`	`32`
`33`		`- nvkm_mask(device, 0x61c5bc + hoff, 0x00000003, ctrl);`
	`33`	`+ nvkm_mask(device, 0x61c5bc + soff, 0x00000003, ctrl);`
`34`	`34`
`35`	`35`	`ior->tmds.high_speed = !!(scdc & 0x2);`
`36`	`36`	`}`