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esmilbebarino
esmil
authored and
bebarino
committed
clk: starfive: Add flags argument to JH71X0__MUX macro
This flag is needed to add the CLK_SET_RATE_PARENT flag on the gmac_tx clock on the JH7100, which in turn is needed by the dwmac-starfive driver to set the clock properly for 1000, 100 and 10 Mbps links. This change was mostly made using coccinelle: @ match @ expression idx, name, nparents; @@ JH71X0__MUX( -idx, name, nparents, +idx, name, 0, nparents, ...) Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Cristian Ciocaltea <[email protected]> Reviewed-by: Jacob Keller <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
1 parent b85ea95 commit a242b20

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6 files changed

+36
-36
lines changed

6 files changed

+36
-36
lines changed

‎drivers/clk/starfive/clk-starfive-jh7100-audio.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,7 @@ static const struct jh71x0_clk_data jh7100_audclk_data[] = {
7979
JH71X0_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
8080
JH71X0_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
8181
JH71X0__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
82-
JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
82+
JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 0, 2,
8383
JH7100_AUDCLK_VAD_INTMEM,
8484
JH7100_AUDCLK_AUDIO_12288),
8585
};

‎drivers/clk/starfive/clk-starfive-jh7100.c

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -24,48 +24,48 @@
2424
#define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3)
2525

2626
static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
27-
JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
27+
JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 0, 4,
2828
JH7100_CLK_OSC_SYS,
2929
JH7100_CLK_PLL0_OUT,
3030
JH7100_CLK_PLL1_OUT,
3131
JH7100_CLK_PLL2_OUT),
32-
JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
32+
JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 0, 3,
3333
JH7100_CLK_OSC_SYS,
3434
JH7100_CLK_PLL1_OUT,
3535
JH7100_CLK_PLL2_OUT),
36-
JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
36+
JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 0, 4,
3737
JH7100_CLK_OSC_SYS,
3838
JH7100_CLK_PLL0_OUT,
3939
JH7100_CLK_PLL1_OUT,
4040
JH7100_CLK_PLL2_OUT),
41-
JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
41+
JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 0, 3,
4242
JH7100_CLK_OSC_SYS,
4343
JH7100_CLK_PLL0_OUT,
4444
JH7100_CLK_PLL2_OUT),
45-
JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
45+
JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 0, 2,
4646
JH7100_CLK_OSC_SYS,
4747
JH7100_CLK_PLL0_OUT),
48-
JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
48+
JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 0, 2,
4949
JH7100_CLK_OSC_SYS,
5050
JH7100_CLK_PLL2_OUT),
51-
JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
51+
JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 0, 3,
5252
JH7100_CLK_OSC_SYS,
5353
JH7100_CLK_PLL1_OUT,
5454
JH7100_CLK_PLL2_OUT),
55-
JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
55+
JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 0, 3,
5656
JH7100_CLK_OSC_AUD,
5757
JH7100_CLK_PLL0_OUT,
5858
JH7100_CLK_PLL2_OUT),
5959
JH71X0_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
60-
JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
60+
JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 0, 3,
6161
JH7100_CLK_OSC_SYS,
6262
JH7100_CLK_PLL1_OUT,
6363
JH7100_CLK_PLL2_OUT),
64-
JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
64+
JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 0, 3,
6565
JH7100_CLK_OSC_SYS,
6666
JH7100_CLK_PLL0_OUT,
6767
JH7100_CLK_PLL1_OUT),
68-
JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
68+
JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 0, 3,
6969
JH7100_CLK_OSC_AUD,
7070
JH7100_CLK_PLL0_OUT,
7171
JH7100_CLK_PLL2_OUT),
@@ -76,7 +76,7 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
7676
JH71X0_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
7777
JH71X0_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
7878
JH71X0_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
79-
JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
79+
JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 0, 2,
8080
JH7100_CLK_OSC_SYS,
8181
JH7100_CLK_OSC_AUD),
8282
JH71X0__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
@@ -142,7 +142,7 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
142142
JH71X0__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
143143
JH71X0_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
144144
JH71X0__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
145-
JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
145+
JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 0, 2,
146146
JH7100_CLK_CPU_AXI,
147147
JH7100_CLK_NNEBUS_SRC1),
148148
JH71X0_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
@@ -166,7 +166,7 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
166166
JH71X0_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
167167
JH71X0_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32,
168168
JH7100_CLK_USBPHY_ROOTDIV),
169-
JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
169+
JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 0, 2,
170170
JH7100_CLK_OSC_SYS,
171171
JH7100_CLK_USBPHY_PLLDIV25M),
172172
JH71X0_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
@@ -200,12 +200,12 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
200200
JH71X0_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
201201
JH71X0_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
202202
JH71X0_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
203-
JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
203+
JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 0, 3,
204204
JH7100_CLK_GMAC_GTX,
205205
JH7100_CLK_GMAC_TX_INV,
206206
JH7100_CLK_GMAC_RMII_TX),
207207
JH71X0__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
208-
JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
208+
JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 0, 2,
209209
JH7100_CLK_GMAC_GR_MII_RX,
210210
JH7100_CLK_GMAC_RMII_RX),
211211
JH71X0__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),

‎drivers/clk/starfive/clk-starfive-jh7110-aon.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626
static const struct jh71x0_clk_data jh7110_aonclk_data[] = {
2727
/* source */
2828
JH71X0__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC),
29-
JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2,
29+
JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 0, 2,
3030
JH7110_AONCLK_OSC_DIV4,
3131
JH7110_AONCLK_OSC),
3232
/* gmac0 */
@@ -39,7 +39,7 @@ static const struct jh71x0_clk_data jh7110_aonclk_data[] = {
3939
JH7110_AONCLK_GMAC0_GTXCLK,
4040
JH7110_AONCLK_GMAC0_RMII_RTX),
4141
JH71X0__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX),
42-
JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2,
42+
JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 0, 2,
4343
JH7110_AONCLK_GMAC0_RGMII_RXIN,
4444
JH7110_AONCLK_GMAC0_RMII_RTX),
4545
JH71X0__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX),
@@ -48,7 +48,7 @@ static const struct jh71x0_clk_data jh7110_aonclk_data[] = {
4848
/* rtc */
4949
JH71X0_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", 0, JH7110_AONCLK_APB_BUS),
5050
JH71X0__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC),
51-
JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2,
51+
JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 0, 2,
5252
JH7110_AONCLK_RTC_OSC,
5353
JH7110_AONCLK_RTC_INTERNAL),
5454
JH71X0_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC),

‎drivers/clk/starfive/clk-starfive-jh7110-isp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ static const struct jh71x0_clk_data jh7110_ispclk_data[] = {
5353
JH7110_ISPCLK_MIPI_RX0_PXL),
5454
JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", 0,
5555
JH7110_ISPCLK_MIPI_RX0_PXL),
56-
JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 2,
56+
JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 0, 2,
5757
JH7110_ISPCLK_MIPI_RX0_PXL,
5858
JH7110_ISPCLK_DVP_INV),
5959
/* ispv2_top_wrapper */

‎drivers/clk/starfive/clk-starfive-jh7110-sys.c

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -36,18 +36,18 @@
3636

3737
static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
3838
/* root */
39-
JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2,
39+
JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 0, 2,
4040
JH7110_SYSCLK_OSC,
4141
JH7110_SYSCLK_PLL0_OUT),
4242
JH71X0__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT),
4343
JH71X0__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE),
44-
JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2,
44+
JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 0, 2,
4545
JH7110_SYSCLK_PLL2_OUT,
4646
JH7110_SYSCLK_PLL1_OUT),
4747
JH71X0_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2,
4848
JH7110_SYSCLK_PLL0_OUT,
4949
JH7110_SYSCLK_PLL2_OUT),
50-
JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2,
50+
JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 0, 2,
5151
JH7110_SYSCLK_OSC,
5252
JH7110_SYSCLK_PLL2_OUT),
5353
JH71X0__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT),
@@ -62,7 +62,7 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
6262
JH71X0__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT),
6363
JH71X0__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT),
6464
JH71X0__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT),
65-
JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 2,
65+
JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 0, 2,
6666
JH7110_SYSCLK_MCLK_INNER,
6767
JH7110_SYSCLK_MCLK_EXT),
6868
JH71X0_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER),
@@ -96,7 +96,7 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
9696
JH71X0__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC),
9797
JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2),
9898
JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4),
99-
JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4,
99+
JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 0, 4,
100100
JH7110_SYSCLK_OSC_DIV2,
101101
JH7110_SYSCLK_PLL1_DIV2,
102102
JH7110_SYSCLK_PLL1_DIV4,
@@ -186,7 +186,7 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
186186
JH71X0__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30,
187187
JH7110_SYSCLK_GMAC1_RMII_REFIN),
188188
JH71X0_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
189-
JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2,
189+
JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 0, 2,
190190
JH7110_SYSCLK_GMAC1_RGMII_RXIN,
191191
JH7110_SYSCLK_GMAC1_RMII_RTX),
192192
JH71X0__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX),
@@ -270,11 +270,11 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
270270
JH71X0_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2,
271271
JH7110_SYSCLK_I2STX0_BCLK_MST_INV,
272272
JH7110_SYSCLK_I2STX0_BCLK_MST),
273-
JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 2,
273+
JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 0, 2,
274274
JH7110_SYSCLK_I2STX0_BCLK_MST,
275275
JH7110_SYSCLK_I2STX_BCLK_EXT),
276276
JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK),
277-
JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2,
277+
JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 0, 2,
278278
JH7110_SYSCLK_I2STX0_LRCK_MST,
279279
JH7110_SYSCLK_I2STX_LRCK_EXT),
280280
/* i2stx1 */
@@ -285,11 +285,11 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
285285
JH71X0_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2,
286286
JH7110_SYSCLK_I2STX1_BCLK_MST_INV,
287287
JH7110_SYSCLK_I2STX1_BCLK_MST),
288-
JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2,
288+
JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 0, 2,
289289
JH7110_SYSCLK_I2STX1_BCLK_MST,
290290
JH7110_SYSCLK_I2STX_BCLK_EXT),
291291
JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK),
292-
JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2,
292+
JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 0, 2,
293293
JH7110_SYSCLK_I2STX1_LRCK_MST,
294294
JH7110_SYSCLK_I2STX_LRCK_EXT),
295295
/* i2srx */
@@ -300,11 +300,11 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
300300
JH71X0_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2,
301301
JH7110_SYSCLK_I2SRX_BCLK_MST_INV,
302302
JH7110_SYSCLK_I2SRX_BCLK_MST),
303-
JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2,
303+
JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 0, 2,
304304
JH7110_SYSCLK_I2SRX_BCLK_MST,
305305
JH7110_SYSCLK_I2SRX_BCLK_EXT),
306306
JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK),
307-
JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2,
307+
JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 0, 2,
308308
JH7110_SYSCLK_I2SRX_LRCK_MST,
309309
JH7110_SYSCLK_I2SRX_LRCK_EXT),
310310
/* pdm */
@@ -314,7 +314,7 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
314314
JH71X0_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0),
315315
JH71X0_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0),
316316
JH71X0_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK),
317-
JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2,
317+
JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 0, 2,
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JH7110_SYSCLK_TDM_INTERNAL,
319319
JH7110_SYSCLK_TDM_EXT),
320320
JH71X0__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM),

‎drivers/clk/starfive/clk-starfive-jh71x0.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -61,10 +61,10 @@ struct jh71x0_clk_data {
6161
.parents = { [0] = _parent }, \
6262
}
6363

64-
#define JH71X0__MUX(_idx, _name, _nparents, ...) \
64+
#define JH71X0__MUX(_idx, _name, _flags, _nparents, ...) \
6565
[_idx] = { \
6666
.name = _name, \
67-
.flags = 0, \
67+
.flags = _flags, \
6868
.max = ((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT, \
6969
.parents = { __VA_ARGS__ }, \
7070
}

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