@@ -53,6 +53,7 @@ int fsl_ifc_find(phys_addr_t addr_base)
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for (i = 0 ; i < fsl_ifc_ctrl_dev -> banks ; i ++ ) {
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u32 cspr = ifc_in32 (& fsl_ifc_ctrl_dev -> gregs -> cspr_cs [i ].cspr );
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+
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if (cspr & CSPR_V && (cspr & CSPR_BA ) ==
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convert_ifc_address (addr_base ))
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return i ;
@@ -153,8 +154,8 @@ static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
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/* read for chip select error */
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cs_err = ifc_in32 (& ifc -> cm_evter_stat );
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if (cs_err ) {
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- dev_err (ctrl -> dev , "transaction sent to IFC is not mapped to"
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- "any memory bank 0x%08X\n" , cs_err );
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+ dev_err (ctrl -> dev , "transaction sent to IFC is not mapped to any memory bank 0x%08X\n" ,
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+ cs_err );
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/* clear the chip select error */
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ifc_out32 (IFC_CM_EVTER_STAT_CSER , & ifc -> cm_evter_stat );
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@@ -163,24 +164,24 @@ static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
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err_addr = ifc_in32 (& ifc -> cm_erattr1 );
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if (status & IFC_CM_ERATTR0_ERTYP_READ )
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- dev_err (ctrl -> dev , "Read transaction error"
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- "CM_ERATTR0 0x%08X\n" , status );
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+ dev_err (ctrl -> dev , "Read transaction error CM_ERATTR0 0x%08X\n" ,
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+ status );
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else
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- dev_err (ctrl -> dev , "Write transaction error"
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- "CM_ERATTR0 0x%08X\n" , status );
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+ dev_err (ctrl -> dev , "Write transaction error CM_ERATTR0 0x%08X\n" ,
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+ status );
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err_axiid = (status & IFC_CM_ERATTR0_ERAID ) >>
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IFC_CM_ERATTR0_ERAID_SHIFT ;
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- dev_err (ctrl -> dev , "AXI ID of the error"
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- "transaction 0x%08X\n" , err_axiid );
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+ dev_err (ctrl -> dev , "AXI ID of the error transaction 0x%08X\n" ,
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+ err_axiid );
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err_srcid = (status & IFC_CM_ERATTR0_ESRCID ) >>
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IFC_CM_ERATTR0_ESRCID_SHIFT ;
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- dev_err (ctrl -> dev , "SRC ID of the error"
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- "transaction 0x%08X\n" , err_srcid );
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+ dev_err (ctrl -> dev , "SRC ID of the error transaction 0x%08X\n" ,
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+ err_srcid );
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- dev_err (ctrl -> dev , "Transaction Address corresponding to error"
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- "ERADDR 0x%08X\n" , err_addr );
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+ dev_err (ctrl -> dev , "Transaction Address corresponding to error ERADDR 0x%08X\n" ,
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+ err_addr );
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ret = IRQ_HANDLED ;
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}
@@ -199,7 +200,7 @@ static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
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* the resources needed for the controller only. The
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* resources for the NAND banks themselves are allocated
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* in the chip probe function.
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- */
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+ */
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static int fsl_ifc_ctrl_probe (struct platform_device * dev )
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{
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int ret = 0 ;
@@ -250,8 +251,7 @@ static int fsl_ifc_ctrl_probe(struct platform_device *dev)
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/* get the Controller level irq */
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fsl_ifc_ctrl_dev -> irq = irq_of_parse_and_map (dev -> dev .of_node , 0 );
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if (fsl_ifc_ctrl_dev -> irq == 0 ) {
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- dev_err (& dev -> dev , "failed to get irq resource "
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- "for IFC\n" );
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+ dev_err (& dev -> dev , "failed to get irq resource for IFC\n" );
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ret = - ENODEV ;
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goto err ;
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}
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