|
95 | 95 | #define QM_VFT_CFG_RDY 0x10006c
|
96 | 96 | #define QM_VFT_CFG_OP_WR 0x100058
|
97 | 97 | #define QM_VFT_CFG_TYPE 0x10005c
|
98 |
| -#define QM_SQC_VFT 0x0 |
99 |
| -#define QM_CQC_VFT 0x1 |
100 | 98 | #define QM_VFT_CFG 0x100060
|
101 | 99 | #define QM_VFT_CFG_OP_ENABLE 0x100054
|
102 | 100 | #define QM_PM_CTRL 0x100148
|
|
164 | 162 |
|
165 | 163 | /* interfunction communication */
|
166 | 164 | #define QM_IFC_READY_STATUS 0x100128
|
167 |
| -#define QM_IFC_C_STS_M 0x10012C |
168 | 165 | #define QM_IFC_INT_SET_P 0x100130
|
169 | 166 | #define QM_IFC_INT_CFG 0x100134
|
170 | 167 | #define QM_IFC_INT_SOURCE_P 0x100138
|
|
198 | 195 |
|
199 | 196 | #define PCI_BAR_2 2
|
200 | 197 | #define PCI_BAR_4 4
|
201 |
| -#define QM_SQE_DATA_ALIGN_MASK GENMASK(6, 0) |
202 | 198 | #define QMC_ALIGN(sz) ALIGN(sz, 32)
|
203 | 199 |
|
204 | 200 | #define QM_DBG_READ_LEN 256
|
|
212 | 208 | #define QM_DRIVER_REMOVING 0
|
213 | 209 | #define QM_RST_SCHED 1
|
214 | 210 | #define QM_QOS_PARAM_NUM 2
|
215 |
| -#define QM_QOS_VAL_NUM 1 |
216 |
| -#define QM_QOS_BDF_PARAM_NUM 4 |
217 | 211 | #define QM_QOS_MAX_VAL 1000
|
218 | 212 | #define QM_QOS_RATE 100
|
219 | 213 | #define QM_QOS_EXPAND_RATE 1000
|
|
225 | 219 | #define QM_SHAPER_FACTOR_CBS_B_SHIFT 15
|
226 | 220 | #define QM_SHAPER_FACTOR_CBS_S_SHIFT 19
|
227 | 221 | #define QM_SHAPER_CBS_B 1
|
228 |
| -#define QM_SHAPER_CBS_S 16 |
229 | 222 | #define QM_SHAPER_VFT_OFFSET 6
|
230 |
| -#define WAIT_FOR_QOS_VF 100 |
231 | 223 | #define QM_QOS_MIN_ERROR_RATE 5
|
232 |
| -#define QM_QOS_TYPICAL_NUM 8 |
233 | 224 | #define QM_SHAPER_MIN_CBS_S 8
|
234 | 225 | #define QM_QOS_TICK 0x300U
|
235 | 226 | #define QM_QOS_DIVISOR_CLK 0x1f40U
|
236 | 227 | #define QM_QOS_MAX_CIR_B 200
|
237 | 228 | #define QM_QOS_MIN_CIR_B 100
|
238 | 229 | #define QM_QOS_MAX_CIR_U 6
|
239 |
| -#define QM_QOS_MAX_CIR_S 11 |
240 | 230 | #define QM_AUTOSUSPEND_DELAY 3000
|
241 | 231 |
|
242 | 232 | #define QM_MK_CQC_DW3_V1(hop_num, pg_sz, buf_sz, cqe_sz) \
|
|
0 commit comments