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37 | 37 | #define CLK_SOURCE_LA 0x1f8
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38 | 38 | #define CLK_SOURCE_SDMMC2 0x154
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39 | 39 | #define CLK_SOURCE_SDMMC4 0x164
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| 40 | +#define CLK_SOURCE_EMC_DLL 0x664 |
40 | 41 |
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41 | 42 | #define PLLC_BASE 0x80
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42 | 43 | #define PLLC_OUT 0x84
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227 | 228 | #define RST_DFLL_DVCO 0x2f4
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228 | 229 | #define DVFS_DFLL_RESET_SHIFT 0
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229 | 230 |
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| 231 | +#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET 0x284 |
| 232 | +#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR 0x288 |
| 233 | +#define CLK_OUT_ENB_X_CLK_ENB_EMC_DLL BIT(14) |
| 234 | + |
230 | 235 | #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
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231 | 236 | #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
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232 | 237 | #define CPU_SOFTRST_CTRL 0x380
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@@ -555,6 +560,27 @@ void tegra210_set_sata_pll_seq_sw(bool state)
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555 | 560 | }
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556 | 561 | EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw);
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557 | 562 |
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| 563 | +void tegra210_clk_emc_dll_enable(bool flag) |
| 564 | +{ |
| 565 | + u32 offset = flag ? CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET : |
| 566 | + CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR; |
| 567 | + |
| 568 | + writel_relaxed(CLK_OUT_ENB_X_CLK_ENB_EMC_DLL, clk_base + offset); |
| 569 | +} |
| 570 | +EXPORT_SYMBOL_GPL(tegra210_clk_emc_dll_enable); |
| 571 | + |
| 572 | +void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value) |
| 573 | +{ |
| 574 | + writel_relaxed(emc_dll_src_value, clk_base + CLK_SOURCE_EMC_DLL); |
| 575 | +} |
| 576 | +EXPORT_SYMBOL_GPL(tegra210_clk_emc_dll_update_setting); |
| 577 | + |
| 578 | +void tegra210_clk_emc_update_setting(u32 emc_src_value) |
| 579 | +{ |
| 580 | + writel_relaxed(emc_src_value, clk_base + CLK_SOURCE_EMC); |
| 581 | +} |
| 582 | +EXPORT_SYMBOL_GPL(tegra210_clk_emc_update_setting); |
| 583 | + |
558 | 584 | static void tegra210_generic_mbist_war(struct tegra210_domain_mbist_war *mbist)
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559 | 585 | {
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560 | 586 | u32 val;
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