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Merge tag 'renesas-drivers-for-v5.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers
Renesas driver updates for v5.9 - Add core support for the new RZ/G2H (R8A774E1) SoC, including System Controller (SYSC) and Reset (RST) support. * tag 'renesas-drivers-for-v5.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: rcar-rst: Add support for RZ/G2H soc: renesas: Identify RZ/G2H soc: renesas: Add Renesas R8A774E1 config option soc: renesas: rcar-sysc: Add r8a774e1 support clk: renesas: Add r8a774e1 CPG Core Clock Definitions dt-bindings: power: Add r8a774e1 SYSC power domain definitions Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
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‎drivers/soc/renesas/Kconfig

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@@ -201,6 +201,13 @@ config ARCH_R8A774C0
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help
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This enables support for the Renesas RZ/G2E SoC.
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config ARCH_R8A774E1
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bool "Renesas RZ/G2H SoC Platform"
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select ARCH_RCAR_GEN3
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select SYSC_R8A774E1
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help
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This enables support for the Renesas RZ/G2H SoC.
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config ARCH_R8A77950
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bool "Renesas R-Car H3 ES1.x SoC Platform"
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select ARCH_RCAR_GEN3
@@ -296,6 +303,10 @@ config SYSC_R8A774C0
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bool "RZ/G2E System Controller support" if COMPILE_TEST
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select SYSC_RCAR
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config SYSC_R8A774E1
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bool "RZ/G2H System Controller support" if COMPILE_TEST
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select SYSC_RCAR
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config SYSC_R8A7779
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bool "R-Car H1 System Controller support" if COMPILE_TEST
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select SYSC_RCAR

‎drivers/soc/renesas/Makefile

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@@ -10,6 +10,7 @@ obj-$(CONFIG_SYSC_R8A77470) += r8a77470-sysc.o
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obj-$(CONFIG_SYSC_R8A774A1) += r8a774a1-sysc.o
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obj-$(CONFIG_SYSC_R8A774B1) += r8a774b1-sysc.o
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obj-$(CONFIG_SYSC_R8A774C0) += r8a774c0-sysc.o
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obj-$(CONFIG_SYSC_R8A774E1) += r8a774e1-sysc.o
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obj-$(CONFIG_SYSC_R8A7779) += r8a7779-sysc.o
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obj-$(CONFIG_SYSC_R8A7790) += r8a7790-sysc.o
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obj-$(CONFIG_SYSC_R8A7791) += r8a7791-sysc.o

‎drivers/soc/renesas/r8a774e1-sysc.c

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@@ -0,0 +1,43 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/G2H System Controller
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* Copyright (C) 2020 Renesas Electronics Corp.
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*
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* Based on Renesas R-Car H3 System Controller
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* Copyright (C) 2016-2017 Glider bvba
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*/
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#include <linux/kernel.h>
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#include <dt-bindings/power/r8a774e1-sysc.h>
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#include "rcar-sysc.h"
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static const struct rcar_sysc_area r8a774e1_areas[] __initconst = {
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{ "always-on", 0, 0, R8A774E1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
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{ "ca57-scu", 0x1c0, 0, R8A774E1_PD_CA57_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU },
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{ "ca57-cpu0", 0x80, 0, R8A774E1_PD_CA57_CPU0, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
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{ "ca57-cpu1", 0x80, 1, R8A774E1_PD_CA57_CPU1, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
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{ "ca57-cpu2", 0x80, 2, R8A774E1_PD_CA57_CPU2, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
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{ "ca57-cpu3", 0x80, 3, R8A774E1_PD_CA57_CPU3, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
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{ "ca53-scu", 0x140, 0, R8A774E1_PD_CA53_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU },
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{ "ca53-cpu0", 0x200, 0, R8A774E1_PD_CA53_CPU0, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },
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{ "ca53-cpu1", 0x200, 1, R8A774E1_PD_CA53_CPU1, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },
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{ "ca53-cpu2", 0x200, 2, R8A774E1_PD_CA53_CPU2, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },
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{ "ca53-cpu3", 0x200, 3, R8A774E1_PD_CA53_CPU3, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },
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{ "a3vp", 0x340, 0, R8A774E1_PD_A3VP, R8A774E1_PD_ALWAYS_ON },
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{ "a3vc", 0x380, 0, R8A774E1_PD_A3VC, R8A774E1_PD_ALWAYS_ON },
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{ "a2vc1", 0x3c0, 1, R8A774E1_PD_A2VC1, R8A774E1_PD_A3VC },
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{ "3dg-a", 0x100, 0, R8A774E1_PD_3DG_A, R8A774E1_PD_ALWAYS_ON },
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{ "3dg-b", 0x100, 1, R8A774E1_PD_3DG_B, R8A774E1_PD_3DG_A },
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{ "3dg-c", 0x100, 2, R8A774E1_PD_3DG_C, R8A774E1_PD_3DG_B },
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{ "3dg-d", 0x100, 3, R8A774E1_PD_3DG_D, R8A774E1_PD_3DG_C },
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{ "3dg-e", 0x100, 4, R8A774E1_PD_3DG_E, R8A774E1_PD_3DG_D },
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};
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const struct rcar_sysc_info r8a774e1_sysc_info __initconst = {
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.areas = r8a774e1_areas,
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.num_areas = ARRAY_SIZE(r8a774e1_areas),
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.extmask_offs = 0x2f8,
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.extmask_val = BIT(0),
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};

‎drivers/soc/renesas/rcar-rst.c

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@@ -48,6 +48,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
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{ .compatible = "renesas,r8a774a1-rst", .data = &rcar_rst_gen3 },
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{ .compatible = "renesas,r8a774b1-rst", .data = &rcar_rst_gen3 },
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{ .compatible = "renesas,r8a774c0-rst", .data = &rcar_rst_gen3 },
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{ .compatible = "renesas,r8a774e1-rst", .data = &rcar_rst_gen3 },
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/* R-Car Gen1 */
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{ .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 },
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{ .compatible = "renesas,r8a7779-reset-wdt", .data = &rcar_rst_gen1 },

‎drivers/soc/renesas/rcar-sysc.c

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@@ -296,6 +296,9 @@ static const struct of_device_id rcar_sysc_matches[] __initconst = {
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#ifdef CONFIG_SYSC_R8A774C0
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{ .compatible = "renesas,r8a774c0-sysc", .data = &r8a774c0_sysc_info },
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#endif
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#ifdef CONFIG_SYSC_R8A774E1
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{ .compatible = "renesas,r8a774e1-sysc", .data = &r8a774e1_sysc_info },
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#endif
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#ifdef CONFIG_SYSC_R8A7779
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{ .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
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#endif

‎drivers/soc/renesas/rcar-sysc.h

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@@ -56,6 +56,7 @@ extern const struct rcar_sysc_info r8a77470_sysc_info;
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extern const struct rcar_sysc_info r8a774a1_sysc_info;
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extern const struct rcar_sysc_info r8a774b1_sysc_info;
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extern const struct rcar_sysc_info r8a774c0_sysc_info;
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extern const struct rcar_sysc_info r8a774e1_sysc_info;
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extern const struct rcar_sysc_info r8a7779_sysc_info;
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extern const struct rcar_sysc_info r8a7790_sysc_info;
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extern const struct rcar_sysc_info r8a7791_sysc_info;

‎drivers/soc/renesas/renesas-soc.c

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@@ -126,6 +126,11 @@ static const struct renesas_soc soc_rz_g2e __initconst __maybe_unused = {
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.id = 0x57,
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};
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static const struct renesas_soc soc_rz_g2h __initconst __maybe_unused = {
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.family = &fam_rzg2,
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.id = 0x4f,
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};
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static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = {
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.family = &fam_rcar_gen1,
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};
@@ -238,6 +243,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
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#ifdef CONFIG_ARCH_R8A774C0
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{ .compatible = "renesas,r8a774c0", .data = &soc_rz_g2e },
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#endif
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#ifdef CONFIG_ARCH_R8A774E1
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{ .compatible = "renesas,r8a774e1", .data = &soc_rz_g2h },
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#endif
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#ifdef CONFIG_ARCH_R8A7778
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{ .compatible = "renesas,r8a7778", .data = &soc_rcar_m1a },
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#endif

‎include/dt-bindings/clock/r8a774e1-cpg-mssr.h

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/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* R8A774E1 CPG Core Clocks */
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#define R8A774E1_CLK_Z 0
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#define R8A774E1_CLK_Z2 1
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#define R8A774E1_CLK_ZG 2
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#define R8A774E1_CLK_ZTR 3
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#define R8A774E1_CLK_ZTRD2 4
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#define R8A774E1_CLK_ZT 5
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#define R8A774E1_CLK_ZX 6
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#define R8A774E1_CLK_S0D1 7
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#define R8A774E1_CLK_S0D2 8
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#define R8A774E1_CLK_S0D3 9
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#define R8A774E1_CLK_S0D4 10
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#define R8A774E1_CLK_S0D6 11
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#define R8A774E1_CLK_S0D8 12
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#define R8A774E1_CLK_S0D12 13
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#define R8A774E1_CLK_S1D2 14
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#define R8A774E1_CLK_S1D4 15
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#define R8A774E1_CLK_S2D1 16
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#define R8A774E1_CLK_S2D2 17
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#define R8A774E1_CLK_S2D4 18
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#define R8A774E1_CLK_S3D1 19
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#define R8A774E1_CLK_S3D2 20
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#define R8A774E1_CLK_S3D4 21
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#define R8A774E1_CLK_LB 22
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#define R8A774E1_CLK_CL 23
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#define R8A774E1_CLK_ZB3 24
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#define R8A774E1_CLK_ZB3D2 25
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#define R8A774E1_CLK_ZB3D4 26
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#define R8A774E1_CLK_CR 27
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#define R8A774E1_CLK_CRD2 28
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#define R8A774E1_CLK_SD0H 29
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#define R8A774E1_CLK_SD0 30
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#define R8A774E1_CLK_SD1H 31
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#define R8A774E1_CLK_SD1 32
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#define R8A774E1_CLK_SD2H 33
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#define R8A774E1_CLK_SD2 34
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#define R8A774E1_CLK_SD3H 35
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#define R8A774E1_CLK_SD3 36
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#define R8A774E1_CLK_RPC 37
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#define R8A774E1_CLK_RPCD2 38
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#define R8A774E1_CLK_MSO 39
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#define R8A774E1_CLK_HDMI 40
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#define R8A774E1_CLK_CSI0 41
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#define R8A774E1_CLK_CP 42
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#define R8A774E1_CLK_CPEX 43
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#define R8A774E1_CLK_R 44
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#define R8A774E1_CLK_OSC 45
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#define R8A774E1_CLK_CANFD 46
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#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */

‎include/dt-bindings/power/r8a774e1-sysc.h

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/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
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#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
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/*
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* These power domain indices match the numbers of the interrupt bits
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* representing the power areas in the various Interrupt Registers
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* (e.g. SYSCISR, Interrupt Status Register)
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*/
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#define R8A774E1_PD_CA57_CPU0 0
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#define R8A774E1_PD_CA57_CPU1 1
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#define R8A774E1_PD_CA57_CPU2 2
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#define R8A774E1_PD_CA57_CPU3 3
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#define R8A774E1_PD_CA53_CPU0 5
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#define R8A774E1_PD_CA53_CPU1 6
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#define R8A774E1_PD_CA53_CPU2 7
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#define R8A774E1_PD_CA53_CPU3 8
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#define R8A774E1_PD_A3VP 9
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#define R8A774E1_PD_CA57_SCU 12
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#define R8A774E1_PD_A3VC 14
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#define R8A774E1_PD_3DG_A 17
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#define R8A774E1_PD_3DG_B 18
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#define R8A774E1_PD_3DG_C 19
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#define R8A774E1_PD_3DG_D 20
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#define R8A774E1_PD_CA53_SCU 21
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#define R8A774E1_PD_3DG_E 22
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#define R8A774E1_PD_A2VC1 26
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/* Always-on power area */
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#define R8A774E1_PD_ALWAYS_ON 32
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#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */

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