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danish-tir-vignesh
danish-ti
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r-vignesh
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arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
The IDK application board has 4 Gigabit Ethernet ports. This patch adds support for the 4 Gigabit Ethernet ports which are provided by ICSSG0 and ICSSG1. The IEP0 SYNC_OUT0 pins are used for PPS out on the IDK card. Signed-off-by: MD Danish Anwar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vignesh Raghavendra <[email protected]>
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‎arch/arm64/boot/dts/ti/Makefile

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@@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-wlan.dtb
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# Boards with AM65x SoC
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k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo
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k3-am654-evm-dtbs := k3-am654-base-board.dtb k3-am654-icssg2.dtbo
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k3-am654-idk-dtbs := k3-am654-evm.dtb k3-am654-idk.dtbo
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dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb
@@ -55,6 +56,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am654-evm.dtb
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dtb-$(CONFIG_ARCH_K3) += k3-am654-idk.dtb
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# Boards with J7200 SoC
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k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo

‎arch/arm64/boot/dts/ti/k3-am654-idk.dtso

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// SPDX-License-Identifier: GPL-2.0
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/**
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* DT overlay for IDK application board on AM654 EVM
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*
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* Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/net/ti-dp83867.h>
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#include "k3-pinctrl.h"
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&{/} {
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aliases {
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ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
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ethernet4 = "/icssg0-eth/ethernet-ports/port@1";
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ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
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ethernet6 = "/icssg1-eth/ethernet-ports/port@1";
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};
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/* Ethernet node on PRU-ICSSG0 */
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icssg0_eth: icssg0-eth {
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compatible = "ti,am654-icssg-prueth";
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pinctrl-names = "default";
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pinctrl-0 = <&icssg0_rgmii_pins_default>;
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sram = <&msmc_ram>;
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ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
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firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
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"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
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"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
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"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
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"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
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"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
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ti,pruss-gp-mux-sel = <2>, /* MII mode */
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<2>,
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<2>,
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<2>, /* MII mode */
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<2>,
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<2>;
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ti,mii-g-rt = <&icssg0_mii_g_rt>;
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ti,mii-rt = <&icssg0_mii_rt>;
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ti,iep = <&icssg0_iep0>, <&icssg0_iep1>;
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interrupt-parent = <&icssg0_intc>;
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interrupts = <24 0 2>, <25 1 3>;
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interrupt-names = "tx_ts0", "tx_ts1";
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dmas = <&main_udmap 0xc100>, /* egress slice 0 */
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<&main_udmap 0xc101>, /* egress slice 0 */
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<&main_udmap 0xc102>, /* egress slice 0 */
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<&main_udmap 0xc103>, /* egress slice 0 */
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<&main_udmap 0xc104>, /* egress slice 1 */
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<&main_udmap 0xc105>, /* egress slice 1 */
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<&main_udmap 0xc106>, /* egress slice 1 */
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<&main_udmap 0xc107>, /* egress slice 1 */
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<&main_udmap 0x4100>, /* ingress slice 0 */
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<&main_udmap 0x4101>, /* ingress slice 1 */
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<&main_udmap 0x4102>, /* mgmnt rsp slice 0 */
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<&main_udmap 0x4103>; /* mgmnt rsp slice 1 */
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dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
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"tx1-0", "tx1-1", "tx1-2", "tx1-3",
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"rx0", "rx1";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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icssg0_emac0: port@0 {
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reg = <0>;
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phy-handle = <&icssg0_phy0>;
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phy-mode = "rgmii-id";
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ti,syscon-rgmii-delay = <&scm_conf 0x4100>;
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/* Filled in by bootloader */
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local-mac-address = [00 00 00 00 00 00];
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};
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icssg0_emac1: port@1 {
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reg = <1>;
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phy-handle = <&icssg0_phy1>;
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phy-mode = "rgmii-id";
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ti,syscon-rgmii-delay = <&scm_conf 0x4104>;
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/* Filled in by bootloader */
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local-mac-address = [00 00 00 00 00 00];
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};
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};
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};
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/* Ethernet node on PRU-ICSSG1 */
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icssg1_eth: icssg1-eth {
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compatible = "ti,am654-icssg-prueth";
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pinctrl-names = "default";
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pinctrl-0 = <&icssg1_rgmii_pins_default>;
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sram = <&msmc_ram>;
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ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
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firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
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"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
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"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
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"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
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"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
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"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
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ti,pruss-gp-mux-sel = <2>, /* MII mode */
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<2>,
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<2>,
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<2>, /* MII mode */
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<2>,
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<2>;
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ti,mii-g-rt = <&icssg1_mii_g_rt>;
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ti,mii-rt = <&icssg1_mii_rt>;
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ti,iep = <&icssg1_iep0>, <&icssg1_iep1>;
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interrupt-parent = <&icssg1_intc>;
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interrupts = <24 0 2>, <25 1 3>;
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interrupt-names = "tx_ts0", "tx_ts1";
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dmas = <&main_udmap 0xc200>, /* egress slice 0 */
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<&main_udmap 0xc201>, /* egress slice 0 */
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<&main_udmap 0xc202>, /* egress slice 0 */
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<&main_udmap 0xc203>, /* egress slice 0 */
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<&main_udmap 0xc204>, /* egress slice 1 */
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<&main_udmap 0xc205>, /* egress slice 1 */
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<&main_udmap 0xc206>, /* egress slice 1 */
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<&main_udmap 0xc207>, /* egress slice 1 */
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<&main_udmap 0x4200>, /* ingress slice 0 */
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<&main_udmap 0x4201>, /* ingress slice 1 */
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<&main_udmap 0x4202>, /* mgmnt rsp slice 0 */
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<&main_udmap 0x4203>; /* mgmnt rsp slice 1 */
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dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
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"tx1-0", "tx1-1", "tx1-2", "tx1-3",
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"rx0", "rx1";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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icssg1_emac0: port@0 {
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reg = <0>;
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phy-handle = <&icssg1_phy0>;
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phy-mode = "rgmii-id";
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ti,syscon-rgmii-delay = <&scm_conf 0x4110>;
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/* Filled in by bootloader */
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local-mac-address = [00 00 00 00 00 00];
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};
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icssg1_emac1: port@1 {
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reg = <1>;
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phy-handle = <&icssg1_phy1>;
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phy-mode = "rgmii-id";
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ti,syscon-rgmii-delay = <&scm_conf 0x4114>;
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/* Filled in by bootloader */
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local-mac-address = [00 00 00 00 00 00];
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};
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};
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};
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};
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&main_pmx0 {
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icssg0_mdio_pins_default: icssg0-mdio-default-pins {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x0294, PIN_INPUT, 0) /* (AE26) PRG0_MDIO0_MDIO */
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AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28) PRG0_MDIO0_MDC */
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>;
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};
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icssg0_rgmii_pins_default: icssg0-rgmii-default-pins {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x0244, PIN_INPUT, 2) /* (AB28) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
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AM65X_IOPAD(0x0248, PIN_INPUT, 2) /* (AC28) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
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AM65X_IOPAD(0x024c, PIN_INPUT, 2) /* (AC27) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
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AM65X_IOPAD(0x0250, PIN_INPUT, 2) /* (AB26) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
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AM65X_IOPAD(0x0274, PIN_OUTPUT, 2) /* (AC25) PRG0_PRU1_GPO12.PRG0_RGMII2_TD0 */
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AM65X_IOPAD(0x0278, PIN_OUTPUT, 2) /* (AD25) PRG0_PRU1_GPO13.PRG0_RGMII2_TD1 */
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AM65X_IOPAD(0x027c, PIN_OUTPUT, 2) /* (AD24) PRG0_PRU1_GPO14.PRG0_RGMII2_TD2 */
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AM65X_IOPAD(0x0280, PIN_OUTPUT, 2) /* (AE27) PRG0_PRU1_GPO15.PRG0_RGMII2_TD3 */
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AM65X_IOPAD(0x0284, PIN_INPUT, 2) /* (AC24) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
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AM65X_IOPAD(0x0270, PIN_OUTPUT, 2) /* (AB24) PRG0_PRU1_GPO11.PRG0_RGMII2_TX_CTL */
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AM65X_IOPAD(0x025c, PIN_INPUT, 2) /* (AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
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AM65X_IOPAD(0x0254, PIN_INPUT, 2) /* (AA25) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
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AM65X_IOPAD(0x01f4, PIN_INPUT, 2) /* (V24) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
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AM65X_IOPAD(0x01f8, PIN_INPUT, 2) /* (W25) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
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AM65X_IOPAD(0x01fc, PIN_INPUT, 2) /* (W24) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
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AM65X_IOPAD(0x0200, PIN_INPUT, 2) /* (AA27) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
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AM65X_IOPAD(0x0224, PIN_OUTPUT, 2) /* (AD27) PRG0_PRU0_GPO12.PRG0_RGMII1_TD0 */
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AM65X_IOPAD(0x0228, PIN_OUTPUT, 2) /* (AC26) PRG0_PRU0_GPO13.PRG0_RGMII1_TD1 */
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AM65X_IOPAD(0x022c, PIN_OUTPUT, 2) /* (AD26) PRG0_PRU0_GPO14.PRG0_RGMII1_TD2 */
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AM65X_IOPAD(0x0230, PIN_OUTPUT, 2) /* (AA24) PRG0_PRU0_GPO15.PRG0_RGMII1_TD3 */
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AM65X_IOPAD(0x0234, PIN_INPUT, 2) /* (AD28) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
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AM65X_IOPAD(0x0220, PIN_OUTPUT, 2) /* (AB25) PRG0_PRU0_GPO11.PRG0_RGMII1_TX_CTL */
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AM65X_IOPAD(0x020c, PIN_INPUT, 2) /* (Y25) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
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AM65X_IOPAD(0x0204, PIN_INPUT, 2) /* (Y24) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
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>;
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};
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icssg0_iep0_pins_default: icssg0-iep0-default-pins {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x0240, PIN_INPUT, 2) /* (U24) PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */
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>;
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};
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icssg1_mdio_pins_default: icssg1-mdio-default-pins {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x0180, PIN_INPUT, 0) /* (AD18) PRG1_MDIO0_MDIO */
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AM65X_IOPAD(0x0184, PIN_OUTPUT, 0) /* (AH18) PRG1_MDIO0_MDC */
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>;
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};
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icssg1_rgmii_pins_default: icssg1-rgmii-default-pins {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x0130, PIN_INPUT, 2) /* (AH24) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */
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AM65X_IOPAD(0x0134, PIN_INPUT, 2) /* (AH23) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */
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AM65X_IOPAD(0x0138, PIN_INPUT, 2) /* (AG21) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */
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AM65X_IOPAD(0x013c, PIN_INPUT, 2) /* (AH22) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */
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AM65X_IOPAD(0x0160, PIN_OUTPUT, 2) /* (AE20) PRG1_PRU1_GPO12.PRG1_RGMII2_TD0 */
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AM65X_IOPAD(0x0164, PIN_OUTPUT, 2) /* (AF19) PRG1_PRU1_GPO13.PRG1_RGMII2_TD1 */
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AM65X_IOPAD(0x0168, PIN_OUTPUT, 2) /* (AH19) PRG1_PRU1_GPO14.PRG1_RGMII2_TD2 */
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AM65X_IOPAD(0x016c, PIN_OUTPUT, 2) /* (AG19) PRG1_PRU1_GPO15.PRG1_RGMII2_TD3 */
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AM65X_IOPAD(0x0170, PIN_INPUT, 2) /* (AE19) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */
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AM65X_IOPAD(0x015c, PIN_OUTPUT, 2) /* (AC20) PRG1_PRU1_GPO11.PRG1_RGMII2_TX_CTL */
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AM65X_IOPAD(0x0148, PIN_INPUT, 2) /* (AG22) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */
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AM65X_IOPAD(0x0140, PIN_INPUT, 2) /* (AE21) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */
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AM65X_IOPAD(0x00e0, PIN_INPUT, 2) /* (AE22) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */
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AM65X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AG24) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */
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AM65X_IOPAD(0x00e8, PIN_INPUT, 2) /* (AF23) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */
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AM65X_IOPAD(0x00ec, PIN_INPUT, 2) /* (AD21) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */
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AM65X_IOPAD(0x0110, PIN_OUTPUT, 2) /* (AH20) PRG1_PRU0_GPO12.PRG1_RGMII1_TD0 */
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AM65X_IOPAD(0x0114, PIN_OUTPUT, 2) /* (AH21) PRG1_PRU0_GPO13.PRG1_RGMII1_TD1 */
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AM65X_IOPAD(0x0118, PIN_OUTPUT, 2) /* (AG20) PRG1_PRU0_GPO14.PRG1_RGMII1_TD2 */
233+
AM65X_IOPAD(0x011c, PIN_OUTPUT, 2) /* (AD19) PRG1_PRU0_GPO15.PRG1_RGMII1_TD3 */
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AM65X_IOPAD(0x0120, PIN_INPUT, 2) /* (AD20) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */
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AM65X_IOPAD(0x010c, PIN_OUTPUT, 2) /* (AF21) PRG1_PRU0_GPO11.PRG1_RGMII1_TX_CTL */
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AM65X_IOPAD(0x00f8, PIN_INPUT, 2) /* (AF22) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */
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AM65X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AG23) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */
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>;
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};
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icssg1_iep0_pins_default: icssg1-iep0-default-pins {
242+
pinctrl-single,pins = <
243+
AM65X_IOPAD(0x012c, PIN_INPUT, 2) /* (AG26) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
244+
>;
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};
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};
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&icssg0_mdio {
249+
status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&icssg0_mdio_pins_default>;
252+
#address-cells = <1>;
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#size-cells = <0>;
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icssg0_phy0: ethernet-phy@0 {
256+
reg = <0>;
257+
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
258+
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
259+
};
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icssg0_phy1: ethernet-phy@3 {
262+
reg = <3>;
263+
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
264+
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
265+
};
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};
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&icssg0_iep0 {
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pinctrl-names = "default";
270+
pinctrl-0 = <&icssg0_iep0_pins_default>;
271+
};
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&icssg1_mdio {
274+
status = "okay";
275+
pinctrl-names = "default";
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pinctrl-0 = <&icssg1_mdio_pins_default>;
277+
#address-cells = <1>;
278+
#size-cells = <0>;
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icssg1_phy0: ethernet-phy@0 {
281+
reg = <0>;
282+
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
283+
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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icssg1_phy1: ethernet-phy@3 {
287+
reg = <3>;
288+
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
289+
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
290+
};
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};
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&icssg1_iep0 {
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pinctrl-names = "default";
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pinctrl-0 = <&icssg1_iep0_pins_default>;
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};

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