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Merge tag 'pinctrl-v5.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij: "Some late pin control fixes, the most generally annoying will probably be the AMD IRQ storm fix affecting the Microsoft surface. Summary: - Three fixes pertaining to Broadcom DT bindings. Some stuff didn't work out as inteded, we need to back out - A resume bug fix in the STM32 driver - Disable and mask the interrupts on probe in the AMD pinctrl driver, affecting Microsoft surface" * tag 'pinctrl-v5.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: amd: disable and mask interrupts on probe pinctrl: stm32: use valid pin identifier in stm32_pinctrl_resume() Revert "pinctrl: bcm: ns: support updated DT binding as syscon subnode" dt-bindings: pinctrl: brcm,ns-pinmux: drop unneeded CRU from example Revert "dt-bindings: pinctrl: bcm4708-pinmux: rework binding to use syscon"
2 parents 87066fd + 4e5a04b commit a51aec4

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5 files changed

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Documentation/devicetree/bindings/mfd/brcm,cru.yaml

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -32,13 +32,13 @@ properties:
3232
"#size-cells":
3333
const: 1
3434

35-
pinctrl:
36-
$ref: ../pinctrl/brcm,ns-pinmux.yaml
37-
3835
patternProperties:
3936
'^clock-controller@[a-f0-9]+$':
4037
$ref: ../clock/brcm,iproc-clocks.yaml
4138

39+
'^pin-controller@[a-f0-9]+$':
40+
$ref: ../pinctrl/brcm,ns-pinmux.yaml
41+
4242
'^thermal@[a-f0-9]+$':
4343
$ref: ../thermal/brcm,ns-thermal.yaml
4444

@@ -73,9 +73,10 @@ examples:
7373
"iprocfast", "sata1", "sata2";
7474
};
7575
76-
pinctrl {
76+
pin-controller@1c0 {
7777
compatible = "brcm,bcm4708-pinmux";
78-
offset = <0x1c0>;
78+
reg = <0x1c0 0x24>;
79+
reg-names = "cru_gpio_control";
7980
};
8081
8182
thermal@2c0 {

Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml

Lines changed: 14 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -17,20 +17,18 @@ description:
1717

1818
A list of pins varies across chipsets so few bindings are available.
1919

20-
Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon"
21-
node.
22-
2320
properties:
2421
compatible:
2522
enum:
2623
- brcm,bcm4708-pinmux
2724
- brcm,bcm4709-pinmux
2825
- brcm,bcm53012-pinmux
2926

30-
offset:
31-
description: offset of pin registers in the CRU block
27+
reg:
3228
maxItems: 1
33-
$ref: /schemas/types.yaml#/definitions/uint32-array
29+
30+
reg-names:
31+
const: cru_gpio_control
3432

3533
patternProperties:
3634
'-pins$':
@@ -72,23 +70,20 @@ allOf:
7270
uart1_grp ]
7371

7472
required:
75-
- offset
73+
- reg
74+
- reg-names
7675

7776
additionalProperties: false
7877

7978
examples:
8079
- |
81-
cru@1800c100 {
82-
compatible = "syscon", "simple-mfd";
83-
reg = <0x1800c100 0x1a4>;
84-
85-
pinctrl {
86-
compatible = "brcm,bcm4708-pinmux";
87-
offset = <0xc0>;
88-
89-
spi-pins {
90-
function = "spi";
91-
groups = "spi_grp";
92-
};
80+
pin-controller@1800c1c0 {
81+
compatible = "brcm,bcm4708-pinmux";
82+
reg = <0x1800c1c0 0x24>;
83+
reg-names = "cru_gpio_control";
84+
85+
spi-pins {
86+
function = "spi";
87+
groups = "spi_grp";
9388
};
9489
};

drivers/pinctrl/bcm/pinctrl-ns.c

Lines changed: 10 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -5,15 +5,13 @@
55

66
#include <linux/err.h>
77
#include <linux/io.h>
8-
#include <linux/mfd/syscon.h>
98
#include <linux/module.h>
109
#include <linux/of.h>
1110
#include <linux/of_device.h>
1211
#include <linux/pinctrl/pinconf-generic.h>
1312
#include <linux/pinctrl/pinctrl.h>
1413
#include <linux/pinctrl/pinmux.h>
1514
#include <linux/platform_device.h>
16-
#include <linux/regmap.h>
1715
#include <linux/slab.h>
1816

1917
#define FLAG_BCM4708 BIT(1)
@@ -24,8 +22,7 @@ struct ns_pinctrl {
2422
struct device *dev;
2523
unsigned int chipset_flag;
2624
struct pinctrl_dev *pctldev;
27-
struct regmap *regmap;
28-
u32 offset;
25+
void __iomem *base;
2926

3027
struct pinctrl_desc pctldesc;
3128
struct ns_pinctrl_group *groups;
@@ -232,9 +229,9 @@ static int ns_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev,
232229
unset |= BIT(pin_number);
233230
}
234231

235-
regmap_read(ns_pinctrl->regmap, ns_pinctrl->offset, &tmp);
232+
tmp = readl(ns_pinctrl->base);
236233
tmp &= ~unset;
237-
regmap_write(ns_pinctrl->regmap, ns_pinctrl->offset, tmp);
234+
writel(tmp, ns_pinctrl->base);
238235

239236
return 0;
240237
}
@@ -266,13 +263,13 @@ static const struct of_device_id ns_pinctrl_of_match_table[] = {
266263
static int ns_pinctrl_probe(struct platform_device *pdev)
267264
{
268265
struct device *dev = &pdev->dev;
269-
struct device_node *np = dev->of_node;
270266
const struct of_device_id *of_id;
271267
struct ns_pinctrl *ns_pinctrl;
272268
struct pinctrl_desc *pctldesc;
273269
struct pinctrl_pin_desc *pin;
274270
struct ns_pinctrl_group *group;
275271
struct ns_pinctrl_function *function;
272+
struct resource *res;
276273
int i;
277274

278275
ns_pinctrl = devm_kzalloc(dev, sizeof(*ns_pinctrl), GFP_KERNEL);
@@ -290,18 +287,12 @@ static int ns_pinctrl_probe(struct platform_device *pdev)
290287
return -EINVAL;
291288
ns_pinctrl->chipset_flag = (uintptr_t)of_id->data;
292289

293-
ns_pinctrl->regmap = syscon_node_to_regmap(of_get_parent(np));
294-
if (IS_ERR(ns_pinctrl->regmap)) {
295-
int err = PTR_ERR(ns_pinctrl->regmap);
296-
297-
dev_err(dev, "Failed to map pinctrl regs: %d\n", err);
298-
299-
return err;
300-
}
301-
302-
if (of_property_read_u32(np, "offset", &ns_pinctrl->offset)) {
303-
dev_err(dev, "Failed to get register offset\n");
304-
return -ENOENT;
290+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
291+
"cru_gpio_control");
292+
ns_pinctrl->base = devm_ioremap_resource(dev, res);
293+
if (IS_ERR(ns_pinctrl->base)) {
294+
dev_err(dev, "Failed to map pinctrl regs\n");
295+
return PTR_ERR(ns_pinctrl->base);
305296
}
306297

307298
memcpy(pctldesc, &ns_pinctrl_desc, sizeof(*pctldesc));

drivers/pinctrl/pinctrl-amd.c

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -840,6 +840,34 @@ static const struct pinconf_ops amd_pinconf_ops = {
840840
.pin_config_group_set = amd_pinconf_group_set,
841841
};
842842

843+
static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
844+
{
845+
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
846+
unsigned long flags;
847+
u32 pin_reg, mask;
848+
int i;
849+
850+
mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
851+
BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
852+
BIT(WAKE_CNTRL_OFF_S4);
853+
854+
for (i = 0; i < desc->npins; i++) {
855+
int pin = desc->pins[i].number;
856+
const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
857+
858+
if (!pd)
859+
continue;
860+
861+
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
862+
863+
pin_reg = readl(gpio_dev->base + i * 4);
864+
pin_reg &= ~mask;
865+
writel(pin_reg, gpio_dev->base + i * 4);
866+
867+
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
868+
}
869+
}
870+
843871
#ifdef CONFIG_PM_SLEEP
844872
static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
845873
{
@@ -976,6 +1004,9 @@ static int amd_gpio_probe(struct platform_device *pdev)
9761004
return PTR_ERR(gpio_dev->pctrl);
9771005
}
9781006

1007+
/* Disable and mask interrupts */
1008+
amd_gpio_irq_init(gpio_dev);
1009+
9791010
girq = &gpio_dev->gc.irq;
9801011
girq->chip = &amd_gpio_irqchip;
9811012
/* This will let us handle the parent IRQ in the driver */

drivers/pinctrl/stm32/pinctrl-stm32.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1644,8 +1644,8 @@ int __maybe_unused stm32_pinctrl_resume(struct device *dev)
16441644
struct stm32_pinctrl_group *g = pctl->groups;
16451645
int i;
16461646

1647-
for (i = g->pin; i < g->pin + pctl->ngroups; i++)
1648-
stm32_pinctrl_restore_gpio_regs(pctl, i);
1647+
for (i = 0; i < pctl->ngroups; i++, g++)
1648+
stm32_pinctrl_restore_gpio_regs(pctl, g->pin);
16491649

16501650
return 0;
16511651
}

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