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lines changed Original file line number Diff line number Diff line change @@ -154,7 +154,7 @@ config ARC_CPU_HS
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help
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Support for ARC HS38x Cores based on ARCv2 ISA
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The notable features are:
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- - SMP configurations of upto 4 core with coherency
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+ - SMP configurations of up to 4 cores with coherency
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- Optional L2 Cache and IO-Coherency
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- Revised Interrupt Architecture (multiple priorites, reg banks,
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auto stack switch, auto regfile save/restore)
@@ -192,7 +192,7 @@ config ARC_SMP_HALT_ON_RESET
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help
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In SMP configuration cores can be configured as Halt-on-reset
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or they could all start at same time. For Halt-on-reset, non
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- masters are parked until Master kicks them so they can start of
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+ masters are parked until Master kicks them so they can start off
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at designated entry point. For other case, all jump to common
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entry point and spin wait for Master's signal.
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