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mfd: stm32-timers: Unify alignment of register definition
Use tabs consistently for indention and properly align register names, values and comments. This improves readability (at least for my eyes). Signed-off-by: Uwe Kleine-König <[email protected]> Link: https://lore.kernel.org/r/da3b7f9af5794d7463aa62cbaa7251abf1af2018.1718791090.git.u.kleine-koenig@baylibre.com Signed-off-by: Lee Jones <[email protected]>
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‎include/linux/mfd/stm32-timers.h

Lines changed: 85 additions & 85 deletions
Original file line numberDiff line numberDiff line change
@@ -12,97 +12,97 @@
1212
#include <linux/dma-mapping.h>
1313
#include <linux/regmap.h>
1414

15-
#define TIM_CR1 0x00 /* Control Register 1 */
16-
#define TIM_CR2 0x04 /* Control Register 2 */
17-
#define TIM_SMCR 0x08 /* Slave mode control reg */
18-
#define TIM_DIER 0x0C /* DMA/interrupt register */
19-
#define TIM_SR 0x10 /* Status register */
20-
#define TIM_EGR 0x14 /* Event Generation Reg */
21-
#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
22-
#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
23-
#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
24-
#define TIM_CNT 0x24 /* Counter */
25-
#define TIM_PSC 0x28 /* Prescaler */
26-
#define TIM_ARR 0x2c /* Auto-Reload Register */
27-
#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
28-
#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
29-
#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
30-
#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
31-
#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
32-
#define TIM_DCR 0x48 /* DMA control register */
33-
#define TIM_DMAR 0x4C /* DMA register for transfer */
34-
#define TIM_TISEL 0x68 /* Input Selection */
15+
#define TIM_CR1 0x00 /* Control Register 1 */
16+
#define TIM_CR2 0x04 /* Control Register 2 */
17+
#define TIM_SMCR 0x08 /* Slave mode control reg */
18+
#define TIM_DIER 0x0C /* DMA/interrupt register */
19+
#define TIM_SR 0x10 /* Status register */
20+
#define TIM_EGR 0x14 /* Event Generation Reg */
21+
#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
22+
#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
23+
#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
24+
#define TIM_CNT 0x24 /* Counter */
25+
#define TIM_PSC 0x28 /* Prescaler */
26+
#define TIM_ARR 0x2c /* Auto-Reload Register */
27+
#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
28+
#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
29+
#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
30+
#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
31+
#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
32+
#define TIM_DCR 0x48 /* DMA control register */
33+
#define TIM_DMAR 0x4C /* DMA register for transfer */
34+
#define TIM_TISEL 0x68 /* Input Selection */
3535

36-
#define TIM_CR1_CEN BIT(0) /* Counter Enable */
37-
#define TIM_CR1_DIR BIT(4) /* Counter Direction */
38-
#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
39-
#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
40-
#define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */
41-
#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
42-
#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
43-
#define TIM_DIER_UIE BIT(0) /* Update interrupt */
44-
#define TIM_DIER_CC1IE BIT(1) /* CC1 Interrupt Enable */
45-
#define TIM_DIER_CC2IE BIT(2) /* CC2 Interrupt Enable */
46-
#define TIM_DIER_CC3IE BIT(3) /* CC3 Interrupt Enable */
47-
#define TIM_DIER_CC4IE BIT(4) /* CC4 Interrupt Enable */
48-
#define TIM_DIER_CC_IE(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */
49-
#define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */
50-
#define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */
51-
#define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */
52-
#define TIM_DIER_CC3DE BIT(11) /* CC3 DMA request Enable */
53-
#define TIM_DIER_CC4DE BIT(12) /* CC4 DMA request Enable */
54-
#define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */
55-
#define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */
56-
#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
57-
#define TIM_SR_CC_IF(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt flag */
58-
#define TIM_EGR_UG BIT(0) /* Update Generation */
59-
#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
60-
#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
61-
#define TIM_CCMR_CC1S (BIT(0) | BIT(1)) /* Capture/compare 1 sel */
62-
#define TIM_CCMR_IC1PSC GENMASK(3, 2) /* Input capture 1 prescaler */
63-
#define TIM_CCMR_CC2S (BIT(8) | BIT(9)) /* Capture/compare 2 sel */
64-
#define TIM_CCMR_IC2PSC GENMASK(11, 10) /* Input capture 2 prescaler */
65-
#define TIM_CCMR_CC1S_TI1 BIT(0) /* IC1/IC3 selects TI1/TI3 */
66-
#define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */
67-
#define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */
68-
#define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */
69-
#define TIM_CCMR_CC3S (BIT(0) | BIT(1)) /* Capture/compare 3 sel */
70-
#define TIM_CCMR_CC4S (BIT(8) | BIT(9)) /* Capture/compare 4 sel */
71-
#define TIM_CCMR_CC3S_TI3 BIT(0) /* IC3 selects TI3 */
72-
#define TIM_CCMR_CC4S_TI4 BIT(8) /* IC4 selects TI4 */
73-
#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
74-
#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
75-
#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
76-
#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
77-
#define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */
78-
#define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */
79-
#define TIM_CCER_CC2NP BIT(7) /* Capt/Comp 2N Polarity */
80-
#define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */
81-
#define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */
82-
#define TIM_CCER_CC3NP BIT(11) /* Capt/Comp 3N Polarity */
83-
#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */
84-
#define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */
85-
#define TIM_CCER_CC4NP BIT(15) /* Capt/Comp 4N Polarity */
86-
#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
87-
#define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */
88-
#define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */
89-
#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
90-
#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
91-
#define TIM_BDTR_BKF(x) (0xf << (16 + (x) * 4))
92-
#define TIM_DCR_DBA GENMASK(4, 0) /* DMA base addr */
93-
#define TIM_DCR_DBL GENMASK(12, 8) /* DMA burst len */
36+
#define TIM_CR1_CEN BIT(0) /* Counter Enable */
37+
#define TIM_CR1_DIR BIT(4) /* Counter Direction */
38+
#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
39+
#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
40+
#define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */
41+
#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
42+
#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
43+
#define TIM_DIER_UIE BIT(0) /* Update interrupt */
44+
#define TIM_DIER_CC1IE BIT(1) /* CC1 Interrupt Enable */
45+
#define TIM_DIER_CC2IE BIT(2) /* CC2 Interrupt Enable */
46+
#define TIM_DIER_CC3IE BIT(3) /* CC3 Interrupt Enable */
47+
#define TIM_DIER_CC4IE BIT(4) /* CC4 Interrupt Enable */
48+
#define TIM_DIER_CC_IE(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */
49+
#define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */
50+
#define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */
51+
#define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */
52+
#define TIM_DIER_CC3DE BIT(11) /* CC3 DMA request Enable */
53+
#define TIM_DIER_CC4DE BIT(12) /* CC4 DMA request Enable */
54+
#define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */
55+
#define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */
56+
#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
57+
#define TIM_SR_CC_IF(x) BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt flag */
58+
#define TIM_EGR_UG BIT(0) /* Update Generation */
59+
#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
60+
#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
61+
#define TIM_CCMR_CC1S (BIT(0) | BIT(1)) /* Capture/compare 1 sel */
62+
#define TIM_CCMR_IC1PSC GENMASK(3, 2) /* Input capture 1 prescaler */
63+
#define TIM_CCMR_CC2S (BIT(8) | BIT(9)) /* Capture/compare 2 sel */
64+
#define TIM_CCMR_IC2PSC GENMASK(11, 10) /* Input capture 2 prescaler */
65+
#define TIM_CCMR_CC1S_TI1 BIT(0) /* IC1/IC3 selects TI1/TI3 */
66+
#define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */
67+
#define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */
68+
#define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */
69+
#define TIM_CCMR_CC3S (BIT(0) | BIT(1)) /* Capture/compare 3 sel */
70+
#define TIM_CCMR_CC4S (BIT(8) | BIT(9)) /* Capture/compare 4 sel */
71+
#define TIM_CCMR_CC3S_TI3 BIT(0) /* IC3 selects TI3 */
72+
#define TIM_CCMR_CC4S_TI4 BIT(8) /* IC4 selects TI4 */
73+
#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
74+
#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
75+
#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
76+
#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
77+
#define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */
78+
#define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */
79+
#define TIM_CCER_CC2NP BIT(7) /* Capt/Comp 2N Polarity */
80+
#define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */
81+
#define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */
82+
#define TIM_CCER_CC3NP BIT(11) /* Capt/Comp 3N Polarity */
83+
#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */
84+
#define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */
85+
#define TIM_CCER_CC4NP BIT(15) /* Capt/Comp 4N Polarity */
86+
#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
87+
#define TIM_BDTR_BKE(x) BIT(12 + (x) * 12) /* Break input enable */
88+
#define TIM_BDTR_BKP(x) BIT(13 + (x) * 12) /* Break input polarity */
89+
#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
90+
#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
91+
#define TIM_BDTR_BKF(x) (0xf << (16 + (x) * 4))
92+
#define TIM_DCR_DBA GENMASK(4, 0) /* DMA base addr */
93+
#define TIM_DCR_DBL GENMASK(12, 8) /* DMA burst len */
9494

95-
#define MAX_TIM_PSC 0xFFFF
96-
#define MAX_TIM_ICPSC 0x3
97-
#define TIM_CR2_MMS_SHIFT 4
98-
#define TIM_CR2_MMS2_SHIFT 20
95+
#define MAX_TIM_PSC 0xFFFF
96+
#define MAX_TIM_ICPSC 0x3
97+
#define TIM_CR2_MMS_SHIFT 4
98+
#define TIM_CR2_MMS2_SHIFT 20
9999
#define TIM_SMCR_SMS_SLAVE_MODE_DISABLED 0 /* counts on internal clock when CEN=1 */
100100
#define TIM_SMCR_SMS_ENCODER_MODE_1 1 /* counts TI1FP1 edges, depending on TI2FP2 level */
101101
#define TIM_SMCR_SMS_ENCODER_MODE_2 2 /* counts TI2FP2 edges, depending on TI1FP1 level */
102102
#define TIM_SMCR_SMS_ENCODER_MODE_3 3 /* counts on both TI1FP1 and TI2FP2 edges */
103-
#define TIM_SMCR_TS_SHIFT 4
104-
#define TIM_BDTR_BKF_MASK 0xF
105-
#define TIM_BDTR_BKF_SHIFT(x) (16 + (x) * 4)
103+
#define TIM_SMCR_TS_SHIFT 4
104+
#define TIM_BDTR_BKF_MASK 0xF
105+
#define TIM_BDTR_BKF_SHIFT(x) (16 + (x) * 4)
106106

107107
enum stm32_timers_dmas {
108108
STM32_TIMERS_DMA_CH1,

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