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mchehabmchehab
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media: atomisp: remove non-used 32-bits consts at system_local
There is an abstraction at the code in order to support 32 or 64 bits address/data length. However, for all Atom chipsets supported by this version, the size is fixed. So, cleanup the mess, removing the uused code and placing the data sizes on a single place. The end goal is to completely remove those local/global headers, replacing them by some ISP-version dependent struct, in order for the driver to decide what version it would need in runtime. Signed-off-by: Mauro Carvalho Chehab <[email protected]>
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5 files changed

+3
-331
lines changed

5 files changed

+3
-331
lines changed

‎drivers/staging/media/atomisp/pci/hive_types.h

Lines changed: 3 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -52,32 +52,14 @@ typedef unsigned short hive_uint16;
5252
typedef unsigned int hive_uint32;
5353
typedef unsigned long long hive_uint64;
5454

55-
/* by default assume 32 bit master port (both data and address) */
56-
#ifndef HRT_DATA_WIDTH
57-
#define HRT_DATA_WIDTH 32
58-
#endif
59-
#ifndef HRT_ADDRESS_WIDTH
60-
#define HRT_ADDRESS_WIDTH 32
61-
#endif
62-
55+
#define HRT_DATA_WIDTH 32
56+
#define HRT_ADDRESS_WIDTH 64
6357
#define HRT_DATA_BYTES (HRT_DATA_WIDTH / 8)
6458
#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH / 8)
59+
#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
6560

66-
#if HRT_DATA_WIDTH == 64
67-
typedef hive_uint64 hrt_data;
68-
#elif HRT_DATA_WIDTH == 32
6961
typedef hive_uint32 hrt_data;
70-
#else
71-
#error data width not supported
72-
#endif
73-
74-
#if HRT_ADDRESS_WIDTH == 64
7562
typedef hive_uint64 hrt_address;
76-
#elif HRT_ADDRESS_WIDTH == 32
77-
typedef hive_uint32 hrt_address;
78-
#else
79-
#error adddres width not supported
80-
#endif
8163

8264
/* use 64 bit addresses in simulation, where possible */
8365
typedef hive_uint64 hive_sim_address;

‎drivers/staging/media/atomisp/pci/isp2400_system_global.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -75,8 +75,6 @@
7575
* Semi global. "HRT" is accessible from SP, but the HRT types do not fully apply
7676
*/
7777
#define HRT_VADDRESS_WIDTH 32
78-
//#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property*/
79-
#define HRT_DATA_WIDTH 32
8078

8179
#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
8280
#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8)

‎drivers/staging/media/atomisp/pci/isp2400_system_local.h

Lines changed: 0 additions & 131 deletions
Original file line numberDiff line numberDiff line change
@@ -24,17 +24,12 @@
2424

2525
#include "system_global.h"
2626

27-
/* HRT assumes 32 by default (see Linux/include/hive_types.h), overrule it in case it is different */
28-
#undef HRT_ADDRESS_WIDTH
29-
#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property */
30-
3127
/* This interface is deprecated */
3228
#include "hive_types.h"
3329

3430
/*
3531
* Cell specific address maps
3632
*/
37-
#if HRT_ADDRESS_WIDTH == 64
3833

3934
#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */
4035

@@ -154,130 +149,4 @@ static const hrt_address RX_BASE[N_RX_ID] = {
154149
(hrt_address)0x0000000000080100ULL
155150
};
156151

157-
#elif HRT_ADDRESS_WIDTH == 32
158-
159-
#define GP_FIFO_BASE ((hrt_address)0x00090104) /* This is NOT a base address */
160-
161-
/* ISP */
162-
static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
163-
(hrt_address)0x00020000UL
164-
};
165-
166-
static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
167-
(hrt_address)0x00200000UL
168-
};
169-
170-
static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
171-
(hrt_address)0x100000UL
172-
};
173-
174-
/* SP */
175-
static const hrt_address SP_CTRL_BASE[N_SP_ID] = {
176-
(hrt_address)0x00010000UL
177-
};
178-
179-
static const hrt_address SP_DMEM_BASE[N_SP_ID] = {
180-
(hrt_address)0x00300000UL
181-
};
182-
183-
/* MMU */
184-
/*
185-
* MMU0_ID: The data MMU
186-
* MMU1_ID: The icache MMU
187-
*/
188-
static const hrt_address MMU_BASE[N_MMU_ID] = {
189-
(hrt_address)0x00070000UL,
190-
(hrt_address)0x000A0000UL
191-
};
192-
193-
/* DMA */
194-
static const hrt_address DMA_BASE[N_DMA_ID] = {
195-
(hrt_address)0x00040000UL
196-
};
197-
198-
/* IRQ */
199-
static const hrt_address IRQ_BASE[N_IRQ_ID] = {
200-
(hrt_address)0x00000500UL,
201-
(hrt_address)0x00030A00UL,
202-
(hrt_address)0x0008C000UL,
203-
(hrt_address)0x00090200UL
204-
};
205-
206-
/*
207-
(hrt_address)0x00000500UL};
208-
*/
209-
210-
/* GDC */
211-
static const hrt_address GDC_BASE[N_GDC_ID] = {
212-
(hrt_address)0x00050000UL,
213-
(hrt_address)0x00060000UL
214-
};
215-
216-
/* FIFO_MONITOR (not a subset of GP_DEVICE) */
217-
static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
218-
(hrt_address)0x00000000UL
219-
};
220-
221-
/*
222-
static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
223-
(hrt_address)0x00000000UL};
224-
225-
static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
226-
(hrt_address)0x00090000UL};
227-
*/
228-
229-
/* GP_DEVICE (single base for all separate GP_REG instances) */
230-
static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
231-
(hrt_address)0x00000000UL
232-
};
233-
234-
/*GP TIMER , all timer registers are inter-twined,
235-
* so, having multiple base addresses for
236-
* different timers does not help*/
237-
static const hrt_address GP_TIMER_BASE =
238-
(hrt_address)0x00000600UL;
239-
240-
/* GPIO */
241-
static const hrt_address GPIO_BASE[N_GPIO_ID] = {
242-
(hrt_address)0x00000400UL
243-
};
244-
245-
/* TIMED_CTRL */
246-
static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
247-
(hrt_address)0x00000100UL
248-
};
249-
250-
/* INPUT_FORMATTER */
251-
static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
252-
(hrt_address)0x00030000UL,
253-
(hrt_address)0x00030200UL,
254-
(hrt_address)0x00030400UL
255-
};
256-
257-
/* (hrt_address)0x00030600UL, */ /* memcpy() */
258-
259-
/* INPUT_SYSTEM */
260-
static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
261-
(hrt_address)0x00080000UL
262-
};
263-
264-
/* (hrt_address)0x00081000UL, */ /* capture A */
265-
/* (hrt_address)0x00082000UL, */ /* capture B */
266-
/* (hrt_address)0x00083000UL, */ /* capture C */
267-
/* (hrt_address)0x00084000UL, */ /* Acquisition */
268-
/* (hrt_address)0x00085000UL, */ /* DMA */
269-
/* (hrt_address)0x00089000UL, */ /* ctrl */
270-
/* (hrt_address)0x0008A000UL, */ /* GP regs */
271-
/* (hrt_address)0x0008B000UL, */ /* FIFO */
272-
/* (hrt_address)0x0008C000UL, */ /* IRQ */
273-
274-
/* RX, the MIPI lane control regs start at offset 0 */
275-
static const hrt_address RX_BASE[N_RX_ID] = {
276-
(hrt_address)0x00080100UL
277-
};
278-
279-
#else
280-
#error "system_local.h: HRT_ADDRESS_WIDTH must be one of {32,64}"
281-
#endif
282-
283152
#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */

‎drivers/staging/media/atomisp/pci/isp2401_system_global.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -85,11 +85,7 @@
8585
* the HRT types do not fully apply
8686
*/
8787
#define HRT_VADDRESS_WIDTH 32
88-
/* Surprise, this is a local property*/
89-
/*#define HRT_ADDRESS_WIDTH 64 */
90-
#define HRT_DATA_WIDTH 32
9188

92-
#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
9389
#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8)
9490

9591
/* The main bus connecting all devices */

‎drivers/staging/media/atomisp/pci/isp2401_system_local.h

Lines changed: 0 additions & 173 deletions
Original file line numberDiff line numberDiff line change
@@ -24,15 +24,12 @@
2424

2525
#include "system_global.h"
2626

27-
#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property */
28-
2927
/* This interface is deprecated */
3028
#include "hive_types.h"
3129

3230
/*
3331
* Cell specific address maps
3432
*/
35-
#if HRT_ADDRESS_WIDTH == 64
3633

3734
#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */
3835

@@ -198,175 +195,5 @@ static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = {
198195
0x00000000000C2C00ULL, /* stream2mmio controller B */
199196
0x00000000000C4C00ULL /* stream2mmio controller C */
200197
};
201-
#elif HRT_ADDRESS_WIDTH == 32
202-
203-
#define GP_FIFO_BASE ((hrt_address)0x00090104) /* This is NOT a base address */
204-
205-
/* ISP */
206-
static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
207-
0x00020000UL
208-
};
209-
210-
static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
211-
0xffffffffUL
212-
};
213-
214-
static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
215-
0xffffffffUL
216-
};
217-
218-
/* SP */
219-
static const hrt_address SP_CTRL_BASE[N_SP_ID] = {
220-
0x00010000UL
221-
};
222-
223-
static const hrt_address SP_DMEM_BASE[N_SP_ID] = {
224-
0x00300000UL
225-
};
226-
227-
/* MMU */
228-
/*
229-
* MMU0_ID: The data MMU
230-
* MMU1_ID: The icache MMU
231-
*/
232-
static const hrt_address MMU_BASE[N_MMU_ID] = {
233-
0x00070000UL,
234-
0x000A0000UL
235-
};
236-
237-
/* DMA */
238-
static const hrt_address DMA_BASE[N_DMA_ID] = {
239-
0x00040000UL
240-
};
241-
242-
static const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID] = {
243-
0x000CA000UL
244-
};
245-
246-
/* IRQ */
247-
static const hrt_address IRQ_BASE[N_IRQ_ID] = {
248-
0x00000500UL,
249-
0x00030A00UL,
250-
0x0008C000UL,
251-
0x00090200UL
252-
};
253-
254-
/*
255-
0x00000500UL};
256-
*/
257-
258-
/* GDC */
259-
static const hrt_address GDC_BASE[N_GDC_ID] = {
260-
0x00050000UL,
261-
0x00060000UL
262-
};
263-
264-
/* FIFO_MONITOR (not a subset of GP_DEVICE) */
265-
static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
266-
0x00000000UL
267-
};
268-
269-
/*
270-
static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
271-
0x00000000UL};
272-
273-
static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
274-
0x00090000UL};
275-
*/
276-
277-
/* GP_DEVICE (single base for all separate GP_REG instances) */
278-
static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
279-
0x00000000UL
280-
};
281-
282-
/*GP TIMER , all timer registers are inter-twined,
283-
* so, having multiple base addresses for
284-
* different timers does not help*/
285-
static const hrt_address GP_TIMER_BASE =
286-
(hrt_address)0x00000600UL;
287-
/* GPIO */
288-
static const hrt_address GPIO_BASE[N_GPIO_ID] = {
289-
0x00000400UL
290-
};
291-
292-
/* TIMED_CTRL */
293-
static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
294-
0x00000100UL
295-
};
296-
297-
/* INPUT_FORMATTER */
298-
static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
299-
0x00030000UL,
300-
0x00030200UL,
301-
0x00030400UL
302-
};
303-
304-
/* 0x00030600UL, */ /* memcpy() */
305-
306-
/* INPUT_SYSTEM */
307-
static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
308-
0x00080000UL
309-
};
310-
311-
/* 0x00081000UL, */ /* capture A */
312-
/* 0x00082000UL, */ /* capture B */
313-
/* 0x00083000UL, */ /* capture C */
314-
/* 0x00084000UL, */ /* Acquisition */
315-
/* 0x00085000UL, */ /* DMA */
316-
/* 0x00089000UL, */ /* ctrl */
317-
/* 0x0008A000UL, */ /* GP regs */
318-
/* 0x0008B000UL, */ /* FIFO */
319-
/* 0x0008C000UL, */ /* IRQ */
320-
321-
/* RX, the MIPI lane control regs start at offset 0 */
322-
static const hrt_address RX_BASE[N_RX_ID] = {
323-
0x00080100UL
324-
};
325-
326-
/* IBUF_CTRL, part of the Input System 2401 */
327-
static const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID] = {
328-
0x000C1800UL, /* ibuf controller A */
329-
0x000C3800UL, /* ibuf controller B */
330-
0x000C5800UL /* ibuf controller C */
331-
};
332-
333-
/* ISYS IRQ Controllers, part of the Input System 2401 */
334-
static const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID] = {
335-
0x000C1400ULL, /* port a */
336-
0x000C3400ULL, /* port b */
337-
0x000C5400ULL /* port c */
338-
};
339-
340-
/* CSI FE, part of the Input System 2401 */
341-
static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = {
342-
0x000C0400UL, /* csi fe controller A */
343-
0x000C2400UL, /* csi fe controller B */
344-
0x000C4400UL /* csi fe controller C */
345-
};
346-
347-
/* CSI BE, part of the Input System 2401 */
348-
static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = {
349-
0x000C0800UL, /* csi be controller A */
350-
0x000C2800UL, /* csi be controller B */
351-
0x000C4800UL /* csi be controller C */
352-
};
353-
354-
/* PIXEL Generator, part of the Input System 2401 */
355-
static const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = {
356-
0x000C1000UL, /* pixel gen controller A */
357-
0x000C3000UL, /* pixel gen controller B */
358-
0x000C5000UL /* pixel gen controller C */
359-
};
360-
361-
/* Stream2MMIO, part of the Input System 2401 */
362-
static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = {
363-
0x000C0C00UL, /* stream2mmio controller A */
364-
0x000C2C00UL, /* stream2mmio controller B */
365-
0x000C4C00UL /* stream2mmio controller C */
366-
};
367-
368-
#else
369-
#error "system_local.h: HRT_ADDRESS_WIDTH must be one of {32,64}"
370-
#endif
371198

372199
#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */

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