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mattropejlahtine-intel
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drm/i915: Add Wa_1408615072 and Wa_1407596294 to icl,ehl
Workaround database indicates we should disable clock gating of both the vsunit and hsunit. Bspec: 33450 Bspec: 33451 Cc: [email protected] Cc: Lucas De Marchi <[email protected]> Cc: Matt Atwood <[email protected]> Cc: Radhakrishna Sripada <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Lucas De Marchi <[email protected]> (cherry picked from commit b9cf9da) Signed-off-by: Joonas Lahtinen <[email protected]>
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drivers/gpu/drm/i915/i915_reg.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4177,7 +4177,9 @@ enum {
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#define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
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#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
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#define VFUNIT_CLKGATE_DIS (1 << 20)
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#define VFUNIT_CLKGATE_DIS REG_BIT(20)
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#define HSUNIT_CLKGATE_DIS REG_BIT(8)
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#define VSUNIT_CLKGATE_DIS REG_BIT(3)
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#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
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#define CGPSF_CLKGATE_DIS (1 << 3)

drivers/gpu/drm/i915/intel_pm.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6565,6 +6565,14 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
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/* WaEnable32PlaneMode:icl */
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I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
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_MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
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/*
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* Wa_1408615072:icl,ehl (vsunit)
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* Wa_1407596294:icl,ehl (hsunit)
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*/
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intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE,
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0, VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
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}
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static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)

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