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| 1 | +# SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | +# Copyright 2019 Linaro Ltd. |
| 3 | +%YAML 1.2 |
| 4 | +--- |
| 5 | +$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml# |
| 6 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 7 | + |
| 8 | +title: QCOM SoC Temperature Sensor (TSENS) |
| 9 | + |
| 10 | +maintainers: |
| 11 | + - Amit Kucheria <[email protected]> |
| 12 | + |
| 13 | +description: | |
| 14 | + QCOM SoCs have TSENS IP to allow temperature measurement. There are currently |
| 15 | + three distinct major versions of the IP that is supported by a single driver. |
| 16 | + The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures |
| 17 | + everything before v1 when there was no versioning information. |
| 18 | +
|
| 19 | +properties: |
| 20 | + compatible: |
| 21 | + oneOf: |
| 22 | + - description: v0.1 of TSENS |
| 23 | + items: |
| 24 | + - enum: |
| 25 | + - qcom,msm8916-tsens |
| 26 | + - qcom,msm8974-tsens |
| 27 | + - const: qcom,tsens-v0_1 |
| 28 | + |
| 29 | + - description: v1 of TSENS |
| 30 | + items: |
| 31 | + - enum: |
| 32 | + - qcom,qcs404-tsens |
| 33 | + - const: qcom,tsens-v1 |
| 34 | + |
| 35 | + - description: v2 of TSENS |
| 36 | + items: |
| 37 | + - enum: |
| 38 | + - qcom,msm8996-tsens |
| 39 | + - qcom,msm8998-tsens |
| 40 | + - qcom,sdm845-tsens |
| 41 | + - const: qcom,tsens-v2 |
| 42 | + |
| 43 | + reg: |
| 44 | + maxItems: 2 |
| 45 | + items: |
| 46 | + - description: TM registers |
| 47 | + - description: SROT registers |
| 48 | + |
| 49 | + nvmem-cells: |
| 50 | + minItems: 1 |
| 51 | + maxItems: 2 |
| 52 | + description: |
| 53 | + Reference to an nvmem node for the calibration data |
| 54 | + |
| 55 | + nvmem-cells-names: |
| 56 | + minItems: 1 |
| 57 | + maxItems: 2 |
| 58 | + items: |
| 59 | + - enum: |
| 60 | + - caldata |
| 61 | + - calsel |
| 62 | + |
| 63 | + "#qcom,sensors": |
| 64 | + allOf: |
| 65 | + - $ref: /schemas/types.yaml#/definitions/uint32 |
| 66 | + - minimum: 1 |
| 67 | + - maximum: 16 |
| 68 | + description: |
| 69 | + Number of sensors enabled on this platform |
| 70 | + |
| 71 | + "#thermal-sensor-cells": |
| 72 | + const: 1 |
| 73 | + description: |
| 74 | + Number of cells required to uniquely identify the thermal sensors. Since |
| 75 | + we have multiple sensors this is set to 1 |
| 76 | + |
| 77 | +allOf: |
| 78 | + - if: |
| 79 | + properties: |
| 80 | + compatible: |
| 81 | + contains: |
| 82 | + enum: |
| 83 | + - qcom,msm8916-tsens |
| 84 | + - qcom,msm8974-tsens |
| 85 | + - qcom,qcs404-tsens |
| 86 | + - qcom,tsens-v0_1 |
| 87 | + - qcom,tsens-v1 |
| 88 | + then: |
| 89 | + properties: |
| 90 | + interrupts: |
| 91 | + items: |
| 92 | + - description: Combined interrupt if upper or lower threshold crossed |
| 93 | + interrupt-names: |
| 94 | + items: |
| 95 | + - const: uplow |
| 96 | + |
| 97 | + else: |
| 98 | + properties: |
| 99 | + interrupts: |
| 100 | + items: |
| 101 | + - description: Combined interrupt if upper or lower threshold crossed |
| 102 | + - description: Interrupt if critical threshold crossed |
| 103 | + interrupt-names: |
| 104 | + items: |
| 105 | + - const: uplow |
| 106 | + - const: critical |
| 107 | + |
| 108 | +required: |
| 109 | + - compatible |
| 110 | + - reg |
| 111 | + - "#qcom,sensors" |
| 112 | + - interrupts |
| 113 | + - interrupt-names |
| 114 | + - "#thermal-sensor-cells" |
| 115 | + |
| 116 | +examples: |
| 117 | + - | |
| 118 | + #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 119 | + // Example 1 (legacy: for pre v1 IP): |
| 120 | + tsens1: thermal-sensor@900000 { |
| 121 | + compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; |
| 122 | + reg = <0x4a9000 0x1000>, /* TM */ |
| 123 | + <0x4a8000 0x1000>; /* SROT */ |
| 124 | +
|
| 125 | + nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; |
| 126 | + nvmem-cell-names = "caldata", "calsel"; |
| 127 | +
|
| 128 | + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
| 129 | + interrupt-names = "uplow"; |
| 130 | +
|
| 131 | + #qcom,sensors = <5>; |
| 132 | + #thermal-sensor-cells = <1>; |
| 133 | + }; |
| 134 | +
|
| 135 | + - | |
| 136 | + #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 137 | + // Example 2 (for any platform containing v1 of the TSENS IP): |
| 138 | + tsens2: thermal-sensor@4a9000 { |
| 139 | + compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; |
| 140 | + reg = <0x004a9000 0x1000>, /* TM */ |
| 141 | + <0x004a8000 0x1000>; /* SROT */ |
| 142 | +
|
| 143 | + nvmem-cells = <&tsens_caldata>; |
| 144 | + nvmem-cell-names = "calib"; |
| 145 | +
|
| 146 | + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; |
| 147 | + interrupt-names = "uplow"; |
| 148 | +
|
| 149 | + #qcom,sensors = <10>; |
| 150 | + #thermal-sensor-cells = <1>; |
| 151 | + }; |
| 152 | +
|
| 153 | + - | |
| 154 | + #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 155 | + // Example 3 (for any platform containing v2 of the TSENS IP): |
| 156 | + tsens3: thermal-sensor@c263000 { |
| 157 | + compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; |
| 158 | + reg = <0xc263000 0x1ff>, |
| 159 | + <0xc222000 0x1ff>; |
| 160 | +
|
| 161 | + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, |
| 162 | + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; |
| 163 | + interrupt-names = "uplow", "critical"; |
| 164 | +
|
| 165 | + #qcom,sensors = <13>; |
| 166 | + #thermal-sensor-cells = <1>; |
| 167 | + }; |
| 168 | +... |
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