@@ -796,7 +796,8 @@ static void pata_macio_reset_hw(struct pata_macio_priv *priv, int resume)
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/* Hook the standard slave config to fixup some HW related alignment
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* restrictions
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*/
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- static int pata_macio_slave_config (struct scsi_device * sdev )
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+ static int pata_macio_device_configure (struct scsi_device * sdev ,
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+ struct queue_limits * lim )
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{
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struct ata_port * ap = ata_shost_to_port (sdev -> host );
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struct pata_macio_priv * priv = ap -> private_data ;
@@ -814,7 +815,7 @@ static int pata_macio_slave_config(struct scsi_device *sdev)
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/* OHare has issues with non cache aligned DMA on some chipsets */
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if (priv -> kind == controller_ohare ) {
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- blk_queue_update_dma_alignment ( sdev -> request_queue , 31 ) ;
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+ lim -> dma_alignment = 31 ;
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blk_queue_update_dma_pad (sdev -> request_queue , 31 );
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/* Tell the world about it */
@@ -829,7 +830,7 @@ static int pata_macio_slave_config(struct scsi_device *sdev)
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/* Shasta and K2 seem to have "issues" with reads ... */
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if (priv -> kind == controller_sh_ata6 || priv -> kind == controller_k2_ata6 ) {
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/* Allright these are bad, apply restrictions */
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- blk_queue_update_dma_alignment ( sdev -> request_queue , 15 ) ;
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+ lim -> dma_alignment = 15 ;
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blk_queue_update_dma_pad (sdev -> request_queue , 15 );
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/* We enable MWI and hack cache line size directly here, this
@@ -918,7 +919,7 @@ static const struct scsi_host_template pata_macio_sht = {
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* use 64K minus 256
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*/
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.max_segment_size = MAX_DBDMA_SEG ,
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- .slave_configure = pata_macio_slave_config ,
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+ .device_configure = pata_macio_device_configure ,
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.sdev_groups = ata_common_sdev_groups ,
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.can_queue = ATA_DEF_QUEUE ,
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.tag_alloc_policy = BLK_TAG_ALLOC_RR ,
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