|
2 | 2 |
|
3 | 3 | .. _perf_index:
|
4 | 4 |
|
5 |
| -===================== |
| 5 | +==== |
| 6 | +Perf |
| 7 | +==== |
| 8 | + |
6 | 9 | Perf Event Attributes
|
7 | 10 | =====================
|
8 | 11 |
|
@@ -88,3 +91,76 @@ exclude_host. However when using !exclude_hv there is a small blackout
|
88 | 91 | window at the guest entry/exit where host events are not captured.
|
89 | 92 |
|
90 | 93 | On VHE systems there are no blackout windows.
|
| 94 | + |
| 95 | +Perf Userspace PMU Hardware Counter Access |
| 96 | +========================================== |
| 97 | + |
| 98 | +Overview |
| 99 | +-------- |
| 100 | +The perf userspace tool relies on the PMU to monitor events. It offers an |
| 101 | +abstraction layer over the hardware counters since the underlying |
| 102 | +implementation is cpu-dependent. |
| 103 | +Arm64 allows userspace tools to have access to the registers storing the |
| 104 | +hardware counters' values directly. |
| 105 | + |
| 106 | +This targets specifically self-monitoring tasks in order to reduce the overhead |
| 107 | +by directly accessing the registers without having to go through the kernel. |
| 108 | + |
| 109 | +How-to |
| 110 | +------ |
| 111 | +The focus is set on the armv8 PMUv3 which makes sure that the access to the pmu |
| 112 | +registers is enabled and that the userspace has access to the relevant |
| 113 | +information in order to use them. |
| 114 | + |
| 115 | +In order to have access to the hardware counters, the global sysctl |
| 116 | +kernel/perf_user_access must first be enabled: |
| 117 | + |
| 118 | +.. code-block:: sh |
| 119 | +
|
| 120 | + echo 1 > /proc/sys/kernel/perf_user_access |
| 121 | +
|
| 122 | +It is necessary to open the event using the perf tool interface with config1:1 |
| 123 | +attr bit set: the sys_perf_event_open syscall returns a fd which can |
| 124 | +subsequently be used with the mmap syscall in order to retrieve a page of memory |
| 125 | +containing information about the event. The PMU driver uses this page to expose |
| 126 | +to the user the hardware counter's index and other necessary data. Using this |
| 127 | +index enables the user to access the PMU registers using the `mrs` instruction. |
| 128 | +Access to the PMU registers is only valid while the sequence lock is unchanged. |
| 129 | +In particular, the PMSELR_EL0 register is zeroed each time the sequence lock is |
| 130 | +changed. |
| 131 | + |
| 132 | +The userspace access is supported in libperf using the perf_evsel__mmap() |
| 133 | +and perf_evsel__read() functions. See `tools/lib/perf/tests/test-evsel.c`_ for |
| 134 | +an example. |
| 135 | + |
| 136 | +About heterogeneous systems |
| 137 | +--------------------------- |
| 138 | +On heterogeneous systems such as big.LITTLE, userspace PMU counter access can |
| 139 | +only be enabled when the tasks are pinned to a homogeneous subset of cores and |
| 140 | +the corresponding PMU instance is opened by specifying the 'type' attribute. |
| 141 | +The use of generic event types is not supported in this case. |
| 142 | + |
| 143 | +Have a look at `tools/perf/arch/arm64/tests/user-events.c`_ for an example. It |
| 144 | +can be run using the perf tool to check that the access to the registers works |
| 145 | +correctly from userspace: |
| 146 | + |
| 147 | +.. code-block:: sh |
| 148 | +
|
| 149 | + perf test -v user |
| 150 | +
|
| 151 | +About chained events and counter sizes |
| 152 | +-------------------------------------- |
| 153 | +The user can request either a 32-bit (config1:0 == 0) or 64-bit (config1:0 == 1) |
| 154 | +counter along with userspace access. The sys_perf_event_open syscall will fail |
| 155 | +if a 64-bit counter is requested and the hardware doesn't support 64-bit |
| 156 | +counters. Chained events are not supported in conjunction with userspace counter |
| 157 | +access. If a 32-bit counter is requested on hardware with 64-bit counters, then |
| 158 | +userspace must treat the upper 32-bits read from the counter as UNKNOWN. The |
| 159 | +'pmc_width' field in the user page will indicate the valid width of the counter |
| 160 | +and should be used to mask the upper bits as needed. |
| 161 | + |
| 162 | +.. Links |
| 163 | +.. _tools/perf/arch/arm64/tests/user-events.c: |
| 164 | + https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/arch/arm64/tests/user-events.c |
| 165 | +.. _tools/lib/perf/tests/test-evsel.c: |
| 166 | + https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/lib/perf/tests/test-evsel.c |
0 commit comments