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Merge tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt: - Support for Sv57-based virtual memory. - Various improvements for the MicroChip PolarFire SOC and the associated Icicle dev board, which should allow upstream kernels to boot without any additional modifications. - An improved memmove() implementation. - Support for the new Ssconfpmf and SBI PMU extensions, which allows for a much more useful perf implementation on RISC-V systems. - Support for restartable sequences. * tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (36 commits) rseq/selftests: Add support for RISC-V RISC-V: Add support for restartable sequence MAINTAINERS: Add entry for RISC-V PMU drivers Documentation: riscv: Remove the old documentation RISC-V: Add sscofpmf extension support RISC-V: Add perf platform driver based on SBI PMU extension RISC-V: Add RISC-V SBI PMU extension definitions RISC-V: Add a simple platform driver for RISC-V legacy perf RISC-V: Add a perf core library for pmu drivers RISC-V: Add CSR encodings for all HPMCOUNTERS RISC-V: Remove the current perf implementation RISC-V: Improve /proc/cpuinfo output for ISA extensions RISC-V: Do no continue isa string parsing without correct XLEN RISC-V: Implement multi-letter ISA extension probing framework RISC-V: Extract multi-letter extension names from "riscv, isa" RISC-V: Minimal parser for "riscv, isa" strings RISC-V: Correctly print supported extensions riscv: Fixed misaligned memory access. Fixed pointer comparison. MAINTAINERS: update riscv/microchip entry riscv: dts: microchip: add new peripherals to icicle kit device tree ...
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‎Documentation/devicetree/bindings/clock/microchip,mpfs.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip PolarFire Clock Control Module Binding
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maintainers:
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- Daire McNamara <[email protected]>
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description: |
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Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
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which gates and enables all peripheral clocks.
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This device tree binding describes 33 gate clocks. Clocks are referenced by
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user nodes by the CLKCFG node phandle and the clock index in the group, from
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0 to 32.
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properties:
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compatible:
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const: microchip,mpfs-clkcfg
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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'#clock-cells':
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const: 1
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description: |
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h
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for the full list of PolarFire clock IDs.
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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additionalProperties: false
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examples:
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# Clock Config node:
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- |
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#include <dt-bindings/clock/microchip,mpfs-clock.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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clkcfg: clock-controller@20002000 {
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compatible = "microchip,mpfs-clkcfg";
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reg = <0x0 0x20002000 0x0 0x1000>;
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clocks = <&ref>;
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#clock-cells = <1>;
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};
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};

‎Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip MPFS GPIO Controller Device Tree Bindings
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maintainers:
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- Conor Dooley <[email protected]>
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properties:
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compatible:
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items:
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- enum:
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- microchip,mpfs-gpio
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reg:
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maxItems: 1
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interrupts:
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description:
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Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
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minItems: 1
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maxItems: 32
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interrupt-controller: true
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clocks:
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maxItems: 1
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"#gpio-cells":
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const: 2
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"#interrupt-cells":
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const: 1
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ngpios:
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description:
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The number of GPIOs available.
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minimum: 1
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maximum: 32
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default: 32
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gpio-controller: true
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required:
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- compatible
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- reg
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- interrupts
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- "#interrupt-cells"
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- interrupt-controller
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- "#gpio-cells"
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- gpio-controller
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- clocks
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additionalProperties: false
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examples:
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- |
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gpio@20122000 {
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compatible = "microchip,mpfs-gpio";
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reg = <0x20122000 0x1000>;
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clocks = <&clkcfg 25>;
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interrupt-parent = <&plic>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts = <53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>,
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<53>, <53>, <53>, <53>;
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};
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...

‎Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml renamed to ‎Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/mailbox/microchip,polarfire-soc-mailbox.yaml#"
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$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
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properties:
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compatible:
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const: microchip,polarfire-soc-mailbox
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const: microchip,mpfs-mailbox
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reg:
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items:
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#address-cells = <2>;
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#size-cells = <2>;
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mbox: mailbox@37020000 {
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compatible = "microchip,polarfire-soc-mailbox";
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compatible = "microchip,mpfs-mailbox";
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reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>;
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interrupt-parent = <&L1>;
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interrupts = <96>;

‎Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip IP corePWM controller bindings
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maintainers:
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- Conor Dooley <[email protected]>
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description: |
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corePWM is an 16 channel pulse width modulator FPGA IP
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https://www.microsemi.com/existing-parts/parts/152118
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allOf:
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- $ref: pwm.yaml#
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properties:
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compatible:
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items:
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- const: microchip,corepwm-rtl-v4
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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"#pwm-cells":
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const: 2
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microchip,sync-update-mask:
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description: |
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Depending on how the IP is instantiated, there are two modes of operation.
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In synchronous mode, all channels are updated at the beginning of the PWM period,
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and in asynchronous mode updates happen as the control registers are written.
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A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous
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mode is possible for each channel, and is set by the bitstream programmed to the
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FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that
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control the duty cycle for channel x have a second "shadow"/buffer reg synthesised.
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At runtime a bit wide register exposed to APB can be used to toggle on/off
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synchronised mode for all channels it has been synthesised for.
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Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
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whether synchronous mode is possible for the PWM channel.
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0
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microchip,dac-mode-mask:
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description: |
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Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates
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a minimum period pulse train whose High/Low average is that of the chosen duty
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cycle. This "DAC" will have far better bandwidth and ripple performance than the
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standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP
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core, set at instantiation and by the bitstream programmed to the FPGA, determines
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whether a given channel operates in regular PWM or DAC mode.
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Each bit corresponds to a PWM channel & represents whether DAC mode is enabled
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for that channel.
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0
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required:
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- compatible
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- reg
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- clocks
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additionalProperties: false
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examples:
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- |
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pwm@41000000 {
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compatible = "microchip,corepwm-rtl-v4";
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microchip,sync-update-mask = /bits/ 32 <0>;
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clocks = <&clkcfg 30>;
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reg = <0x41000000 0xF0>;
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#pwm-cells = <2>;
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};

‎Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
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allOf:
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- $ref: rtc.yaml#
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maintainers:
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- Daire McNamara <[email protected]>
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- Lewis Hanly <[email protected]>
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properties:
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compatible:
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enum:
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- microchip,mpfs-rtc
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: |
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RTC_WAKEUP interrupt
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- description: |
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RTC_MATCH, asserted when the content of the Alarm register is equal
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to that of the RTC's count register.
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: rtc
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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rtc@20124000 {
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compatible = "microchip,mpfs-rtc";
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reg = <0x20124000 0x1000>;
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clocks = <&clkcfg 21>;
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clock-names = "rtc";
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interrupts = <80>, <81>;
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};
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...

‎Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
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maintainers:
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- Conor Dooley <[email protected]>
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description: |
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PolarFire SoC devices include a microcontroller acting as the system controller,
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which provides "services" to the main processor and to the FPGA fabric. These
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services include hardware rng, reprogramming of the FPGA and verfification of the
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eNVM contents etc. More information on these services can be found online, at
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https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html
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Communication with the system controller is done via a mailbox, of which the client
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portion is documented here.
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properties:
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mboxes:
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maxItems: 1
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compatible:
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const: microchip,mpfs-sys-controller
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required:
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- compatible
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- mboxes
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additionalProperties: false
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examples:
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- |
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syscontroller {
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compatible = "microchip,mpfs-sys-controller";
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mboxes = <&mbox 0>;
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};

‎Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml

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