Skip to content

Commit aa70f76

Browse files
Ping-Ke ShihKalle Valo
Ping-Ke Shih
authored and
Kalle Valo
committed
wifi: rtw89: pci: generalize interrupt status bits of interrupt handlers
For WiFi 7, interrupt status registers and their definitions are changed a lot, but the logic is still the same, so define fields to reuse the code. Signed-off-by: Ping-Ke Shih <[email protected]> Signed-off-by: Kalle Valo <[email protected]> Link: https://lore.kernel.org/r/[email protected]
1 parent 9e1aff4 commit aa70f76

File tree

4 files changed

+111
-11
lines changed

4 files changed

+111
-11
lines changed

‎drivers/net/wireless/realtek/rtw89/pci.c

Lines changed: 16 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -696,12 +696,6 @@ void rtw89_pci_recognize_intrs_v1(struct rtw89_dev *rtwdev,
696696
}
697697
EXPORT_SYMBOL(rtw89_pci_recognize_intrs_v1);
698698

699-
static void rtw89_pci_clear_isr0(struct rtw89_dev *rtwdev, u32 isr00)
700-
{
701-
/* write 1 clear */
702-
rtw89_write32(rtwdev, R_AX_PCIE_HISR00, isr00);
703-
}
704-
705699
void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
706700
{
707701
rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs);
@@ -773,20 +767,22 @@ static irqreturn_t rtw89_pci_interrupt_threadfn(int irq, void *dev)
773767
{
774768
struct rtw89_dev *rtwdev = dev;
775769
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
770+
const struct rtw89_pci_info *info = rtwdev->pci_info;
771+
const struct rtw89_pci_gen_def *gen_def = info->gen_def;
776772
struct rtw89_pci_isrs isrs;
777773
unsigned long flags;
778774

779775
spin_lock_irqsave(&rtwpci->irq_lock, flags);
780776
rtw89_chip_recognize_intrs(rtwdev, rtwpci, &isrs);
781777
spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
782778

783-
if (unlikely(isrs.isrs[0] & B_AX_RDU_INT))
779+
if (unlikely(isrs.isrs[0] & gen_def->isr_rdu))
784780
rtw89_pci_isr_rxd_unavail(rtwdev, rtwpci);
785781

786-
if (unlikely(isrs.halt_c2h_isrs & B_AX_HALT_C2H_INT_EN))
782+
if (unlikely(isrs.halt_c2h_isrs & gen_def->isr_halt_c2h))
787783
rtw89_ser_notify(rtwdev, rtw89_mac_get_err_status(rtwdev));
788784

789-
if (unlikely(isrs.halt_c2h_isrs & B_AX_WDT_TIMEOUT_INT_EN))
785+
if (unlikely(isrs.halt_c2h_isrs & gen_def->isr_wdt_timeout))
790786
rtw89_ser_notify(rtwdev, MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT);
791787

792788
if (unlikely(rtwpci->under_recovery))
@@ -3748,17 +3744,19 @@ static int rtw89_pci_napi_poll(struct napi_struct *napi, int budget)
37483744
{
37493745
struct rtw89_dev *rtwdev = container_of(napi, struct rtw89_dev, napi);
37503746
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
3747+
const struct rtw89_pci_info *info = rtwdev->pci_info;
3748+
const struct rtw89_pci_gen_def *gen_def = info->gen_def;
37513749
unsigned long flags;
37523750
int work_done;
37533751

37543752
rtwdev->napi_budget_countdown = budget;
37553753

3756-
rtw89_pci_clear_isr0(rtwdev, B_AX_RPQDMA_INT | B_AX_RPQBD_FULL_INT);
3754+
rtw89_write32(rtwdev, gen_def->isr_clear_rpq.addr, gen_def->isr_clear_rpq.data);
37573755
work_done = rtw89_pci_poll_rpq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown);
37583756
if (work_done == budget)
37593757
return budget;
37603758

3761-
rtw89_pci_clear_isr0(rtwdev, B_AX_RXP1DMA_INT | B_AX_RXDMA_INT | B_AX_RDU_INT);
3759+
rtw89_write32(rtwdev, gen_def->isr_clear_rxq.addr, gen_def->isr_clear_rxq.data);
37623760
work_done += rtw89_pci_poll_rxq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown);
37633761
if (work_done < budget && napi_complete_done(napi, work_done)) {
37643762
spin_lock_irqsave(&rtwpci->irq_lock, flags);
@@ -3836,6 +3834,13 @@ SIMPLE_DEV_PM_OPS(rtw89_pm_ops, rtw89_pci_suspend, rtw89_pci_resume);
38363834
EXPORT_SYMBOL(rtw89_pm_ops);
38373835

38383836
const struct rtw89_pci_gen_def rtw89_pci_gen_ax = {
3837+
.isr_rdu = B_AX_RDU_INT,
3838+
.isr_halt_c2h = B_AX_HALT_C2H_INT_EN,
3839+
.isr_wdt_timeout = B_AX_WDT_TIMEOUT_INT_EN,
3840+
.isr_clear_rpq = {R_AX_PCIE_HISR00, B_AX_RPQDMA_INT | B_AX_RPQBD_FULL_INT},
3841+
.isr_clear_rxq = {R_AX_PCIE_HISR00, B_AX_RXP1DMA_INT | B_AX_RXDMA_INT |
3842+
B_AX_RDU_INT},
3843+
38393844
.mac_pre_init = rtw89_pci_ops_mac_pre_init_ax,
38403845
.mac_pre_deinit = NULL,
38413846
.mac_post_init = rtw89_pci_ops_mac_post_init_ax,

‎drivers/net/wireless/realtek/rtw89/pci.h

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -290,6 +290,62 @@
290290
#define B_BE_RTK_LDO_BIAS_LATENCY_MASK GENMASK(9, 8)
291291
#define B_BE_CLK_REQ_LAT_MASK GENMASK(7, 4)
292292

293+
#define R_BE_PCIE_DMA_ISR 0x30BC
294+
#define B_BE_PCIE_RX_RX1P1_ISR_V1 BIT(23)
295+
#define B_BE_PCIE_RX_RX0P1_ISR_V1 BIT(22)
296+
#define B_BE_PCIE_RX_ROQ1_ISR_V1 BIT(21)
297+
#define B_BE_PCIE_RX_RPQ1_ISR_V1 BIT(20)
298+
#define B_BE_PCIE_RX_RX1P2_ISR_V1 BIT(19)
299+
#define B_BE_PCIE_RX_ROQ0_ISR_V1 BIT(18)
300+
#define B_BE_PCIE_RX_RPQ0_ISR_V1 BIT(17)
301+
#define B_BE_PCIE_RX_RX0P2_ISR_V1 BIT(16)
302+
#define B_BE_PCIE_TX_CH14_ISR BIT(14)
303+
#define B_BE_PCIE_TX_CH13_ISR BIT(13)
304+
#define B_BE_PCIE_TX_CH12_ISR BIT(12)
305+
#define B_BE_PCIE_TX_CH11_ISR BIT(11)
306+
#define B_BE_PCIE_TX_CH10_ISR BIT(10)
307+
#define B_BE_PCIE_TX_CH9_ISR BIT(9)
308+
#define B_BE_PCIE_TX_CH8_ISR BIT(8)
309+
#define B_BE_PCIE_TX_CH7_ISR BIT(7)
310+
#define B_BE_PCIE_TX_CH6_ISR BIT(6)
311+
#define B_BE_PCIE_TX_CH5_ISR BIT(5)
312+
#define B_BE_PCIE_TX_CH4_ISR BIT(4)
313+
#define B_BE_PCIE_TX_CH3_ISR BIT(3)
314+
#define B_BE_PCIE_TX_CH2_ISR BIT(2)
315+
#define B_BE_PCIE_TX_CH1_ISR BIT(1)
316+
#define B_BE_PCIE_TX_CH0_ISR BIT(0)
317+
318+
#define R_BE_HAXI_HISR00 0xB0B4
319+
#define B_BE_RDU_CH6_INT BIT(28)
320+
#define B_BE_RDU_CH5_INT BIT(27)
321+
#define B_BE_RDU_CH4_INT BIT(26)
322+
#define B_BE_RDU_CH2_INT BIT(25)
323+
#define B_BE_RDU_CH1_INT BIT(24)
324+
#define B_BE_RDU_CH0_INT BIT(23)
325+
#define B_BE_RXDMA_STUCK_INT BIT(22)
326+
#define B_BE_TXDMA_STUCK_INT BIT(21)
327+
#define B_BE_TXDMA_CH14_INT BIT(20)
328+
#define B_BE_TXDMA_CH13_INT BIT(19)
329+
#define B_BE_TXDMA_CH12_INT BIT(18)
330+
#define B_BE_TXDMA_CH11_INT BIT(17)
331+
#define B_BE_TXDMA_CH10_INT BIT(16)
332+
#define B_BE_TXDMA_CH9_INT BIT(15)
333+
#define B_BE_TXDMA_CH8_INT BIT(14)
334+
#define B_BE_TXDMA_CH7_INT BIT(13)
335+
#define B_BE_TXDMA_CH6_INT BIT(12)
336+
#define B_BE_TXDMA_CH5_INT BIT(11)
337+
#define B_BE_TXDMA_CH4_INT BIT(10)
338+
#define B_BE_TXDMA_CH3_INT BIT(9)
339+
#define B_BE_TXDMA_CH2_INT BIT(8)
340+
#define B_BE_TXDMA_CH1_INT BIT(7)
341+
#define B_BE_TXDMA_CH0_INT BIT(6)
342+
#define B_BE_RPQ1DMA_INT BIT(5)
343+
#define B_BE_RX1P1DMA_INT BIT(4)
344+
#define B_BE_RX1DMA_INT BIT(3)
345+
#define B_BE_RPQ0DMA_INT BIT(2)
346+
#define B_BE_RX0P1DMA_INT BIT(1)
347+
#define B_BE_RX0DMA_INT BIT(0)
348+
293349
/* TX/RX */
294350
#define R_AX_DRV_FW_HSK_0 0x01B0
295351
#define R_AX_DRV_FW_HSK_1 0x01B4
@@ -1037,6 +1093,12 @@ struct rtw89_pci_bd_ram {
10371093
};
10381094

10391095
struct rtw89_pci_gen_def {
1096+
u32 isr_rdu;
1097+
u32 isr_halt_c2h;
1098+
u32 isr_wdt_timeout;
1099+
struct rtw89_reg2_def isr_clear_rpq;
1100+
struct rtw89_reg2_def isr_clear_rxq;
1101+
10401102
int (*mac_pre_init)(struct rtw89_dev *rtwdev);
10411103
int (*mac_pre_deinit)(struct rtw89_dev *rtwdev);
10421104
int (*mac_post_init)(struct rtw89_dev *rtwdev);

‎drivers/net/wireless/realtek/rtw89/pci_be.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -490,6 +490,12 @@ static int rtw89_pci_lv1rst_start_dma_be(struct rtw89_dev *rtwdev)
490490
}
491491

492492
const struct rtw89_pci_gen_def rtw89_pci_gen_be = {
493+
.isr_rdu = B_BE_RDU_CH1_INT | B_BE_RDU_CH0_INT,
494+
.isr_halt_c2h = B_BE_HALT_C2H_INT,
495+
.isr_wdt_timeout = B_BE_WDT_TIMEOUT_INT,
496+
.isr_clear_rpq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RPQ0_ISR_V1},
497+
.isr_clear_rxq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RX0P2_ISR_V1},
498+
493499
.mac_pre_init = rtw89_pci_ops_mac_pre_init_be,
494500
.mac_pre_deinit = rtw89_pci_ops_mac_pre_deinit_be,
495501
.mac_post_init = rtw89_pci_ops_mac_post_init_be,

‎drivers/net/wireless/realtek/rtw89/reg.h

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3826,6 +3826,33 @@
38263826
#define B_BE_FS_GPIO17_INT_EN BIT(1)
38273827
#define B_BE_FS_GPIO16_INT_EN BIT(0)
38283828

3829+
#define R_BE_HISR0 0x01A4
3830+
#define B_BE_WDT_DATACPU_TIMEOUT_INT BIT(25)
3831+
#define B_BE_HALT_D2H_INT BIT(24)
3832+
#define B_BE_WDT_TIMEOUT_INT BIT(22)
3833+
#define B_BE_HALT_C2H_INT BIT(21)
3834+
#define B_BE_RON_INT BIT(20)
3835+
#define B_BE_PDNINT BIT(19)
3836+
#define B_BE_SPSANA_OCP_INT BIT(18)
3837+
#define B_BE_SPS_OCP_INT BIT(17)
3838+
#define B_BE_BTON_STS_UPDATE_INT BIT(16)
3839+
#define B_BE_GPIOF_INT BIT(15)
3840+
#define B_BE_GPIOE_INT BIT(14)
3841+
#define B_BE_GPIOD_INT BIT(13)
3842+
#define B_BE_GPIOC_INT BIT(12)
3843+
#define B_BE_GPIOB_INT BIT(11)
3844+
#define B_BE_GPIOA_INT BIT(10)
3845+
#define B_BE_GPIO9_INT BIT(9)
3846+
#define B_BE_GPIO8_INT BIT(8)
3847+
#define B_BE_GPIO7_INT BIT(7)
3848+
#define B_BE_GPIO6_INT BIT(6)
3849+
#define B_BE_GPIO5_INT BIT(5)
3850+
#define B_BE_GPIO4_INT BIT(4)
3851+
#define B_BE_GPIO3_INT BIT(3)
3852+
#define B_BE_GPIO2_INT BIT(2)
3853+
#define B_BE_GPIO1_INT BIT(1)
3854+
#define B_BE_GPIO0_INT BIT(0)
3855+
38293856
#define R_BE_WCPU_FW_CTRL 0x01E0
38303857
#define B_BE_RUN_ENV_MASK GENMASK(31, 30)
38313858
#define B_BE_WCPU_FWDL_STATUS_MASK GENMASK(29, 26)

0 commit comments

Comments
 (0)