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konradybcioGeorgi Djakov
konradybcio
authored and
Georgi Djakov
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interconnect: qcom: sm6350: Retire DEFINE_QBCM
The struct definition macros are hard to read and compare, expand them. Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Georgi Djakov <[email protected]>
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‎drivers/interconnect/qcom/sm6350.c

Lines changed: 226 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -1162,31 +1162,232 @@ static struct qcom_icc_node xs_sys_tcu_cfg = {
11621162
.buswidth = 8,
11631163
};
11641164

1165-
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
1166-
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
1167-
DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_thrott_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc);
1168-
DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_emmc, &xm_sdc2, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_sdc2);
1169-
DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc);
1170-
DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
1171-
DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp);
1172-
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
1173-
DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
1174-
DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_icp_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf, &qxm_mdp0);
1175-
DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
1176-
DEFINE_QBCM(bcm_mm3, "MM3", false, &qhm_mnoc_cfg, &qnm_video0, &qnm_video_cvp, &qxm_camnoc_sf);
1177-
DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup0_core_master, &qup1_core_master, &qup0_core_slave, &qup1_core_slave);
1178-
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
1179-
DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu);
1180-
DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
1181-
DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps);
1182-
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
1183-
DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
1184-
DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
1185-
DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
1186-
DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
1187-
DEFINE_QBCM(bcm_sn5, "SN5", false, &qnm_aggre1_noc);
1188-
DEFINE_QBCM(bcm_sn6, "SN6", false, &qnm_aggre2_noc);
1189-
DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_gemnoc);
1165+
static struct qcom_icc_bcm bcm_acv = {
1166+
.name = "ACV",
1167+
.keepalive = false,
1168+
.num_nodes = 1,
1169+
.nodes = { &ebi },
1170+
};
1171+
1172+
static struct qcom_icc_bcm bcm_ce0 = {
1173+
.name = "CE0",
1174+
.keepalive = false,
1175+
.num_nodes = 1,
1176+
.nodes = { &qxm_crypto },
1177+
};
1178+
1179+
static struct qcom_icc_bcm bcm_cn0 = {
1180+
.name = "CN0",
1181+
.keepalive = true,
1182+
.num_nodes = 41,
1183+
.nodes = { &qnm_snoc,
1184+
&xm_qdss_dap,
1185+
&qhs_a1_noc_cfg,
1186+
&qhs_a2_noc_cfg,
1187+
&qhs_ahb2phy0,
1188+
&qhs_aoss,
1189+
&qhs_boot_rom,
1190+
&qhs_camera_cfg,
1191+
&qhs_camera_nrt_thrott_cfg,
1192+
&qhs_camera_rt_throttle_cfg,
1193+
&qhs_clk_ctl,
1194+
&qhs_cpr_cx,
1195+
&qhs_cpr_mx,
1196+
&qhs_crypto0_cfg,
1197+
&qhs_dcc_cfg,
1198+
&qhs_ddrss_cfg,
1199+
&qhs_display_cfg,
1200+
&qhs_display_throttle_cfg,
1201+
&qhs_glm,
1202+
&qhs_gpuss_cfg,
1203+
&qhs_imem_cfg,
1204+
&qhs_ipa,
1205+
&qhs_mnoc_cfg,
1206+
&qhs_mss_cfg,
1207+
&qhs_npu_cfg,
1208+
&qhs_pimem_cfg,
1209+
&qhs_prng,
1210+
&qhs_qdss_cfg,
1211+
&qhs_qm_cfg,
1212+
&qhs_qm_mpu_cfg,
1213+
&qhs_qup0,
1214+
&qhs_qup1,
1215+
&qhs_security,
1216+
&qhs_snoc_cfg,
1217+
&qhs_tcsr,
1218+
&qhs_ufs_mem_cfg,
1219+
&qhs_usb3_0,
1220+
&qhs_venus_cfg,
1221+
&qhs_venus_throttle_cfg,
1222+
&qhs_vsense_ctrl_cfg,
1223+
&srvc_cnoc
1224+
},
1225+
};
1226+
1227+
static struct qcom_icc_bcm bcm_cn1 = {
1228+
.name = "CN1",
1229+
.keepalive = false,
1230+
.num_nodes = 6,
1231+
.nodes = { &xm_emmc,
1232+
&xm_sdc2,
1233+
&qhs_ahb2phy2,
1234+
&qhs_emmc_cfg,
1235+
&qhs_pdm,
1236+
&qhs_sdc2
1237+
},
1238+
};
1239+
1240+
static struct qcom_icc_bcm bcm_co0 = {
1241+
.name = "CO0",
1242+
.keepalive = false,
1243+
.num_nodes = 1,
1244+
.nodes = { &qns_cdsp_gemnoc },
1245+
};
1246+
1247+
static struct qcom_icc_bcm bcm_co2 = {
1248+
.name = "CO2",
1249+
.keepalive = false,
1250+
.num_nodes = 1,
1251+
.nodes = { &qnm_npu },
1252+
};
1253+
1254+
static struct qcom_icc_bcm bcm_co3 = {
1255+
.name = "CO3",
1256+
.keepalive = false,
1257+
.num_nodes = 1,
1258+
.nodes = { &qxm_npu_dsp },
1259+
};
1260+
1261+
static struct qcom_icc_bcm bcm_mc0 = {
1262+
.name = "MC0",
1263+
.keepalive = true,
1264+
.num_nodes = 1,
1265+
.nodes = { &ebi },
1266+
};
1267+
1268+
static struct qcom_icc_bcm bcm_mm0 = {
1269+
.name = "MM0",
1270+
.keepalive = true,
1271+
.num_nodes = 1,
1272+
.nodes = { &qns_mem_noc_hf },
1273+
};
1274+
1275+
static struct qcom_icc_bcm bcm_mm1 = {
1276+
.name = "MM1",
1277+
.keepalive = true,
1278+
.num_nodes = 5,
1279+
.nodes = { &qxm_camnoc_hf0_uncomp,
1280+
&qxm_camnoc_icp_uncomp,
1281+
&qxm_camnoc_sf_uncomp,
1282+
&qxm_camnoc_hf,
1283+
&qxm_mdp0
1284+
},
1285+
};
1286+
1287+
static struct qcom_icc_bcm bcm_mm2 = {
1288+
.name = "MM2",
1289+
.keepalive = false,
1290+
.num_nodes = 1,
1291+
.nodes = { &qns_mem_noc_sf },
1292+
};
1293+
1294+
static struct qcom_icc_bcm bcm_mm3 = {
1295+
.name = "MM3",
1296+
.keepalive = false,
1297+
.num_nodes = 4,
1298+
.nodes = { &qhm_mnoc_cfg, &qnm_video0, &qnm_video_cvp, &qxm_camnoc_sf },
1299+
};
1300+
1301+
static struct qcom_icc_bcm bcm_qup0 = {
1302+
.name = "QUP0",
1303+
.keepalive = false,
1304+
.num_nodes = 4,
1305+
.nodes = { &qup0_core_master, &qup1_core_master, &qup0_core_slave, &qup1_core_slave },
1306+
};
1307+
1308+
static struct qcom_icc_bcm bcm_sh0 = {
1309+
.name = "SH0",
1310+
.keepalive = true,
1311+
.num_nodes = 1,
1312+
.nodes = { &qns_llcc },
1313+
};
1314+
1315+
static struct qcom_icc_bcm bcm_sh2 = {
1316+
.name = "SH2",
1317+
.keepalive = false,
1318+
.num_nodes = 1,
1319+
.nodes = { &acm_sys_tcu },
1320+
};
1321+
1322+
static struct qcom_icc_bcm bcm_sh3 = {
1323+
.name = "SH3",
1324+
.keepalive = false,
1325+
.num_nodes = 1,
1326+
.nodes = { &qnm_cmpnoc },
1327+
};
1328+
1329+
static struct qcom_icc_bcm bcm_sh4 = {
1330+
.name = "SH4",
1331+
.keepalive = false,
1332+
.num_nodes = 1,
1333+
.nodes = { &acm_apps },
1334+
};
1335+
1336+
static struct qcom_icc_bcm bcm_sn0 = {
1337+
.name = "SN0",
1338+
.keepalive = true,
1339+
.num_nodes = 1,
1340+
.nodes = { &qns_gemnoc_sf },
1341+
};
1342+
1343+
static struct qcom_icc_bcm bcm_sn1 = {
1344+
.name = "SN1",
1345+
.keepalive = false,
1346+
.num_nodes = 1,
1347+
.nodes = { &qxs_imem },
1348+
};
1349+
1350+
static struct qcom_icc_bcm bcm_sn2 = {
1351+
.name = "SN2",
1352+
.keepalive = false,
1353+
.num_nodes = 1,
1354+
.nodes = { &qns_gemnoc_gc },
1355+
};
1356+
1357+
static struct qcom_icc_bcm bcm_sn3 = {
1358+
.name = "SN3",
1359+
.keepalive = false,
1360+
.num_nodes = 1,
1361+
.nodes = { &qxs_pimem },
1362+
};
1363+
1364+
static struct qcom_icc_bcm bcm_sn4 = {
1365+
.name = "SN4",
1366+
.keepalive = false,
1367+
.num_nodes = 1,
1368+
.nodes = { &xs_qdss_stm },
1369+
};
1370+
1371+
static struct qcom_icc_bcm bcm_sn5 = {
1372+
.name = "SN5",
1373+
.keepalive = false,
1374+
.num_nodes = 1,
1375+
.nodes = { &qnm_aggre1_noc },
1376+
};
1377+
1378+
static struct qcom_icc_bcm bcm_sn6 = {
1379+
.name = "SN6",
1380+
.keepalive = false,
1381+
.num_nodes = 1,
1382+
.nodes = { &qnm_aggre2_noc },
1383+
};
1384+
1385+
static struct qcom_icc_bcm bcm_sn10 = {
1386+
.name = "SN10",
1387+
.keepalive = false,
1388+
.num_nodes = 1,
1389+
.nodes = { &qnm_gemnoc },
1390+
};
11901391

11911392
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
11921393
&bcm_cn1,

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