Skip to content

Commit ab5c60b

Browse files
torvaldstorvalds
committed
Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto updates from Herbert Xu: "API: - Add support for allocating transforms on a specific NUMA Node - Introduce the flag CRYPTO_ALG_ALLOCATES_MEMORY for storage users Algorithms: - Drop PMULL based ghash on arm64 - Fixes for building with clang on x86 - Add sha256 helper that does the digest in one go - Add SP800-56A rev 3 validation checks to dh Drivers: - Permit users to specify NUMA node in hisilicon/zip - Add support for i.MX6 in imx-rngc - Add sa2ul crypto driver - Add BA431 hwrng driver - Add Ingenic JZ4780 and X1000 hwrng driver - Spread IRQ affinity in inside-secure and marvell/cesa" * 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (157 commits) crypto: sa2ul - Fix inconsistent IS_ERR and PTR_ERR hwrng: core - remove redundant initialization of variable ret crypto: x86/curve25519 - Remove unused carry variables crypto: ingenic - Add hardware RNG for Ingenic JZ4780 and X1000 dt-bindings: RNG: Add Ingenic RNG bindings. crypto: caam/qi2 - add module alias crypto: caam - add more RNG hw error codes crypto: caam/jr - remove incorrect reference to caam_jr_register() crypto: caam - silence .setkey in case of bad key length crypto: caam/qi2 - create ahash shared descriptors only once crypto: caam/qi2 - fix error reporting for caam_hash_alloc crypto: caam - remove deadcode on 32-bit platforms crypto: ccp - use generic power management crypto: xts - Replace memcpy() invocation with simple assignment crypto: marvell/cesa - irq balance crypto: inside-secure - irq balance crypto: ecc - SP800-56A rev 3 local public key validation crypto: dh - SP800-56A rev 3 local public key validation crypto: dh - check validity of Z before export lib/mpi: Add mpi_sub_ui() ...
2 parents 5577416 + 3cbfe80 commit ab5c60b

File tree

257 files changed

+6648
-5497
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

257 files changed

+6648
-5497
lines changed

‎Documentation/core-api/padata.rst

Lines changed: 3 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -27,22 +27,11 @@ padata_instance structure for overall control of how jobs are to be run::
2727

2828
#include <linux/padata.h>
2929

30-
struct padata_instance *padata_alloc_possible(const char *name);
30+
struct padata_instance *padata_alloc(const char *name);
3131

3232
'name' simply identifies the instance.
3333

34-
There are functions for enabling and disabling the instance::
35-
36-
int padata_start(struct padata_instance *pinst);
37-
void padata_stop(struct padata_instance *pinst);
38-
39-
These functions are setting or clearing the "PADATA_INIT" flag; if that flag is
40-
not set, other functions will refuse to work. padata_start() returns zero on
41-
success (flag set) or -EINVAL if the padata cpumask contains no active CPU
42-
(flag not set). padata_stop() clears the flag and blocks until the padata
43-
instance is unused.
44-
45-
Finally, complete padata initialization by allocating a padata_shell::
34+
Then, complete padata initialization by allocating a padata_shell::
4635

4736
struct padata_shell *padata_alloc_shell(struct padata_instance *pinst);
4837

@@ -155,11 +144,10 @@ submitted.
155144
Destroying
156145
----------
157146

158-
Cleaning up a padata instance predictably involves calling the three free
147+
Cleaning up a padata instance predictably involves calling the two free
159148
functions that correspond to the allocation in reverse::
160149

161150
void padata_free_shell(struct padata_shell *ps);
162-
void padata_stop(struct padata_instance *pinst);
163151
void padata_free(struct padata_instance *pinst);
164152

165153
It is the user's responsibility to ensure all outstanding jobs are complete

‎Documentation/crypto/api-intro.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -169,7 +169,7 @@ Portions of this API were derived from the following projects:
169169

170170
and;
171171

172-
Nettle (http://www.lysator.liu.se/~nisse/nettle/)
172+
Nettle (https://www.lysator.liu.se/~nisse/nettle/)
173173
Niels Möller
174174

175175
Original developers of the crypto algorithms:

‎Documentation/crypto/userspace-if.rst

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ user space, however. This includes the difference between synchronous
2323
and asynchronous invocations. The user space API call is fully
2424
synchronous.
2525

26-
[1] http://www.chronox.de/libkcapi.html
26+
[1] https://www.chronox.de/libkcapi.html
2727

2828
User Space API General Remarks
2929
------------------------------
@@ -384,4 +384,4 @@ Please see [1] for libkcapi which provides an easy-to-use wrapper around
384384
the aforementioned Netlink kernel interface. [1] also contains a test
385385
application that invokes all libkcapi API calls.
386386

387-
[1] http://www.chronox.de/libkcapi.html
387+
[1] https://www.chronox.de/libkcapi.html

‎Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml

Lines changed: 76 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,76 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/crypto/ti,sa2ul.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: K3 SoC SA2UL crypto module
8+
9+
maintainers:
10+
- Tero Kristo <[email protected]>
11+
12+
properties:
13+
compatible:
14+
enum:
15+
- ti,j721e-sa2ul
16+
- ti,am654-sa2ul
17+
18+
reg:
19+
maxItems: 1
20+
21+
power-domains:
22+
maxItems: 1
23+
24+
dmas:
25+
items:
26+
- description: TX DMA Channel
27+
- description: RX DMA Channel #1
28+
- description: RX DMA Channel #2
29+
30+
dma-names:
31+
items:
32+
- const: tx
33+
- const: rx1
34+
- const: rx2
35+
36+
dma-coherent: true
37+
38+
"#address-cells":
39+
const: 2
40+
41+
"#size-cells":
42+
const: 2
43+
44+
ranges:
45+
description:
46+
Address translation for the possible RNG child node for SA2UL
47+
48+
patternProperties:
49+
"^rng@[a-f0-9]+$":
50+
type: object
51+
description:
52+
Child RNG node for SA2UL
53+
54+
required:
55+
- compatible
56+
- reg
57+
- power-domains
58+
- dmas
59+
- dma-names
60+
- dma-coherent
61+
62+
additionalProperties: false
63+
64+
examples:
65+
- |
66+
#include <dt-bindings/soc/ti,sci_pm_domain.h>
67+
68+
main_crypto: crypto@4e00000 {
69+
compatible = "ti,j721-sa2ul";
70+
reg = <0x0 0x4e00000 0x0 0x1200>;
71+
power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
72+
dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
73+
<&main_udmap 0x4001>;
74+
dma-names = "tx", "rx1", "rx2";
75+
dma-coherent;
76+
};

‎Documentation/devicetree/bindings/rng/imx-rng.txt

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,9 @@ Required properties:
55
"fsl,imx21-rnga"
66
"fsl,imx31-rnga" (backward compatible with "fsl,imx21-rnga")
77
"fsl,imx25-rngb"
8+
"fsl,imx6sl-rngb" (backward compatible with "fsl,imx25-rngb")
9+
"fsl,imx6sll-rngb" (backward compatible with "fsl,imx25-rngb")
10+
"fsl,imx6ull-rngb" (backward compatible with "fsl,imx25-rngb")
811
"fsl,imx35-rngc"
912
- reg : offset and length of the register set of this block
1013
- interrupts : the interrupt number for the RNG block

‎Documentation/devicetree/bindings/rng/ingenic,rng.yaml

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/rng/ingenic,rng.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Bindings for RNG in Ingenic SoCs
8+
9+
maintainers:
10+
- 周琰杰 (Zhou Yanjie) <[email protected]>
11+
12+
description:
13+
The Random Number Generator in Ingenic SoCs.
14+
15+
properties:
16+
compatible:
17+
enum:
18+
- ingenic,jz4780-rng
19+
- ingenic,x1000-rng
20+
21+
reg:
22+
maxItems: 1
23+
24+
required:
25+
- compatible
26+
- reg
27+
28+
additionalProperties: false
29+
30+
examples:
31+
- |
32+
rng: rng@d8 {
33+
compatible = "ingenic,jz4780-rng";
34+
reg = <0xd8 0x8>;
35+
};
36+
...

‎Documentation/devicetree/bindings/rng/silex-insight,ba431-rng.yaml

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/rng/silex-insight,ba431-rng.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Silex Insight BA431 RNG bindings
8+
9+
description: |
10+
The BA431 hardware random number generator is an IP that is FIPS-140-2/3
11+
certified.
12+
13+
maintainers:
14+
- Olivier Sobrie <[email protected]>
15+
16+
properties:
17+
compatible:
18+
const: silex-insight,ba431-rng
19+
20+
reg:
21+
maxItems: 1
22+
23+
required:
24+
- compatible
25+
- reg
26+
27+
additionalProperties: false
28+
29+
examples:
30+
- |
31+
rng@42800000 {
32+
compatible = "silex-insight,ba431-rng";
33+
reg = <0x42800000 0x1000>;
34+
};
35+
36+
...

‎MAINTAINERS

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -830,11 +830,20 @@ F: include/uapi/rdma/efa-abi.h
830830

831831
AMD CRYPTOGRAPHIC COPROCESSOR (CCP) DRIVER
832832
M: Tom Lendacky <[email protected]>
833+
M: John Allen <[email protected]>
833834
L: [email protected]
834835
S: Supported
835836
F: drivers/crypto/ccp/
836837
F: include/linux/ccp.h
837838

839+
AMD CRYPTOGRAPHIC COPROCESSOR (CCP) DRIVER - SEV SUPPORT
840+
M: Brijesh Singh <[email protected]>
841+
M: Tom Lendacky <[email protected]>
842+
L: [email protected]
843+
S: Supported
844+
F: drivers/crypto/ccp/sev*
845+
F: include/uapi/linux/psp-sev.h
846+
838847
AMD DISPLAY CORE
839848
M: Harry Wentland <[email protected]>
840849
M: Leo Li <[email protected]>

‎arch/arm/crypto/crc32-ce-core.S

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@
3939
* CRC32 polynomial:0x04c11db7(BE)/0xEDB88320(LE)
4040
* PCLMULQDQ is a new instruction in Intel SSE4.2, the reference can be found
4141
* at:
42-
* http://www.intel.com/products/processor/manuals/
42+
* https://www.intel.com/products/processor/manuals/
4343
* Intel(R) 64 and IA-32 Architectures Software Developer's Manual
4444
* Volume 2B: Instruction Set Reference, N-Z
4545
*

‎arch/arm/crypto/ghash-ce-glue.c

Lines changed: 24 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#include <crypto/gf128mul.h>
1717
#include <linux/cpufeature.h>
1818
#include <linux/crypto.h>
19+
#include <linux/jump_label.h>
1920
#include <linux/module.h>
2021

2122
MODULE_DESCRIPTION("GHASH hash function using ARMv8 Crypto Extensions");
@@ -27,12 +28,8 @@ MODULE_ALIAS_CRYPTO("ghash");
2728
#define GHASH_DIGEST_SIZE 16
2829

2930
struct ghash_key {
30-
u64 h[2];
31-
u64 h2[2];
32-
u64 h3[2];
33-
u64 h4[2];
34-
3531
be128 k;
32+
u64 h[][2];
3633
};
3734

3835
struct ghash_desc_ctx {
@@ -46,16 +43,12 @@ struct ghash_async_ctx {
4643
};
4744

4845
asmlinkage void pmull_ghash_update_p64(int blocks, u64 dg[], const char *src,
49-
struct ghash_key const *k,
50-
const char *head);
46+
u64 const h[][2], const char *head);
5147

5248
asmlinkage void pmull_ghash_update_p8(int blocks, u64 dg[], const char *src,
53-
struct ghash_key const *k,
54-
const char *head);
49+
u64 const h[][2], const char *head);
5550

56-
static void (*pmull_ghash_update)(int blocks, u64 dg[], const char *src,
57-
struct ghash_key const *k,
58-
const char *head);
51+
static __ro_after_init DEFINE_STATIC_KEY_FALSE(use_p64);
5952

6053
static int ghash_init(struct shash_desc *desc)
6154
{
@@ -70,7 +63,10 @@ static void ghash_do_update(int blocks, u64 dg[], const char *src,
7063
{
7164
if (likely(crypto_simd_usable())) {
7265
kernel_neon_begin();
73-
pmull_ghash_update(blocks, dg, src, key, head);
66+
if (static_branch_likely(&use_p64))
67+
pmull_ghash_update_p64(blocks, dg, src, key->h, head);
68+
else
69+
pmull_ghash_update_p8(blocks, dg, src, key->h, head);
7470
kernel_neon_end();
7571
} else {
7672
be128 dst = { cpu_to_be64(dg[1]), cpu_to_be64(dg[0]) };
@@ -161,25 +157,26 @@ static int ghash_setkey(struct crypto_shash *tfm,
161157
const u8 *inkey, unsigned int keylen)
162158
{
163159
struct ghash_key *key = crypto_shash_ctx(tfm);
164-
be128 h;
165160

166161
if (keylen != GHASH_BLOCK_SIZE)
167162
return -EINVAL;
168163

169164
/* needed for the fallback */
170165
memcpy(&key->k, inkey, GHASH_BLOCK_SIZE);
171-
ghash_reflect(key->h, &key->k);
166+
ghash_reflect(key->h[0], &key->k);
172167

173-
h = key->k;
174-
gf128mul_lle(&h, &key->k);
175-
ghash_reflect(key->h2, &h);
168+
if (static_branch_likely(&use_p64)) {
169+
be128 h = key->k;
176170

177-
gf128mul_lle(&h, &key->k);
178-
ghash_reflect(key->h3, &h);
171+
gf128mul_lle(&h, &key->k);
172+
ghash_reflect(key->h[1], &h);
179173

180-
gf128mul_lle(&h, &key->k);
181-
ghash_reflect(key->h4, &h);
174+
gf128mul_lle(&h, &key->k);
175+
ghash_reflect(key->h[2], &h);
182176

177+
gf128mul_lle(&h, &key->k);
178+
ghash_reflect(key->h[3], &h);
179+
}
183180
return 0;
184181
}
185182

@@ -195,7 +192,7 @@ static struct shash_alg ghash_alg = {
195192
.base.cra_driver_name = "ghash-ce-sync",
196193
.base.cra_priority = 300 - 1,
197194
.base.cra_blocksize = GHASH_BLOCK_SIZE,
198-
.base.cra_ctxsize = sizeof(struct ghash_key),
195+
.base.cra_ctxsize = sizeof(struct ghash_key) + sizeof(u64[2]),
199196
.base.cra_module = THIS_MODULE,
200197
};
201198

@@ -354,10 +351,10 @@ static int __init ghash_ce_mod_init(void)
354351
if (!(elf_hwcap & HWCAP_NEON))
355352
return -ENODEV;
356353

357-
if (elf_hwcap2 & HWCAP2_PMULL)
358-
pmull_ghash_update = pmull_ghash_update_p64;
359-
else
360-
pmull_ghash_update = pmull_ghash_update_p8;
354+
if (elf_hwcap2 & HWCAP2_PMULL) {
355+
ghash_alg.base.cra_ctxsize += 3 * sizeof(u64[2]);
356+
static_branch_enable(&use_p64);
357+
}
361358

362359
err = crypto_register_shash(&ghash_alg);
363360
if (err)

0 commit comments

Comments
 (0)