Skip to content

Commit abe0254

Browse files
sgoutham-marvelldavem330
sgoutham-marvell
authored and
davem330
committed
octeontx2-pf: Receive packet handling support
Added receive packet handling (NAPI) support, error stats, RX_ALL capability config option to passon error pkts to stack upon user request. In subsequent patches these error stats will be added to ethttool. Signed-off-by: Sunil Goutham <[email protected]> Signed-off-by: David S. Miller <[email protected]>
1 parent 04a21ef commit abe0254

File tree

6 files changed

+349
-3
lines changed

6 files changed

+349
-3
lines changed

‎drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -334,6 +334,7 @@ static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx)
334334
cq->cq_idx = qidx;
335335
if (qidx < pfvf->hw.rx_queues) {
336336
cq->cq_type = CQ_RX;
337+
cq->cint_idx = qidx;
337338
cq->cqe_cnt = qset->rqe_cnt;
338339
} else {
339340
cq->cq_type = CQ_TX;
@@ -364,6 +365,7 @@ static int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx)
364365
aq->cq.qsize = Q_SIZE(cq->cqe_cnt, 4);
365366
aq->cq.caching = 1;
366367
aq->cq.base = cq->cqe->iova;
368+
aq->cq.cint_idx = cq->cint_idx;
367369
aq->cq.avg_level = 255;
368370

369371
if (qidx < pfvf->hw.rx_queues) {

‎drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,46 @@ enum arua_mapped_qtypes {
4141
#define NIX_LF_ERR_VEC 0x81
4242
#define NIX_LF_POISON_VEC 0x82
4343

44+
/* NIX (or NPC) RX errors */
45+
enum otx2_errlvl {
46+
NPC_ERRLVL_RE,
47+
NPC_ERRLVL_LID_LA,
48+
NPC_ERRLVL_LID_LB,
49+
NPC_ERRLVL_LID_LC,
50+
NPC_ERRLVL_LID_LD,
51+
NPC_ERRLVL_LID_LE,
52+
NPC_ERRLVL_LID_LF,
53+
NPC_ERRLVL_LID_LG,
54+
NPC_ERRLVL_LID_LH,
55+
NPC_ERRLVL_NIX = 0x0F,
56+
};
57+
58+
enum otx2_errcodes_re {
59+
/* NPC_ERRLVL_RE errcodes */
60+
ERRCODE_FCS = 0x7,
61+
ERRCODE_FCS_RCV = 0x8,
62+
ERRCODE_UNDERSIZE = 0x10,
63+
ERRCODE_OVERSIZE = 0x11,
64+
ERRCODE_OL2_LEN_MISMATCH = 0x12,
65+
/* NPC_ERRLVL_NIX errcodes */
66+
ERRCODE_OL3_LEN = 0x10,
67+
ERRCODE_OL4_LEN = 0x11,
68+
ERRCODE_OL4_CSUM = 0x12,
69+
ERRCODE_IL3_LEN = 0x20,
70+
ERRCODE_IL4_LEN = 0x21,
71+
ERRCODE_IL4_CSUM = 0x22,
72+
};
73+
74+
/* Driver counted stats */
75+
struct otx2_drv_stats {
76+
atomic_t rx_fcs_errs;
77+
atomic_t rx_oversize_errs;
78+
atomic_t rx_undersize_errs;
79+
atomic_t rx_csum_errs;
80+
atomic_t rx_len_errs;
81+
atomic_t rx_other_errs;
82+
};
83+
4484
struct mbox {
4585
struct otx2_mbox mbox;
4686
struct work_struct mbox_wrk;
@@ -84,6 +124,9 @@ struct otx2_hw {
84124
u16 nix_msixoff; /* Offset of NIX vectors */
85125
char *irq_name;
86126
cpumask_var_t *affinity_mask;
127+
128+
/* Stats */
129+
struct otx2_drv_stats drv_stats;
87130
};
88131

89132
struct otx2_nic {
@@ -431,6 +474,7 @@ void otx2_sqb_flush(struct otx2_nic *pfvf);
431474
dma_addr_t otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
432475
gfp_t gfp);
433476
void otx2_ctx_disable(struct mbox *mbox, int type, bool npa);
477+
void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq);
434478

435479
/* Mbox handlers */
436480
void mbox_handler_msix_offset(struct otx2_nic *pfvf,

‎drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -547,9 +547,11 @@ static int otx2_init_hw_resources(struct otx2_nic *pf)
547547

548548
static void otx2_free_hw_resources(struct otx2_nic *pf)
549549
{
550+
struct otx2_qset *qset = &pf->qset;
550551
struct mbox *mbox = &pf->mbox;
552+
struct otx2_cq_queue *cq;
551553
struct msg_req *req;
552-
int err;
554+
int qidx, err;
553555

554556
/* Ensure all SQE are processed */
555557
otx2_sqb_flush(pf);
@@ -562,6 +564,13 @@ static void otx2_free_hw_resources(struct otx2_nic *pf)
562564
/* Disable RQs */
563565
otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false);
564566

567+
/*Dequeue all CQEs */
568+
for (qidx = 0; qidx < qset->cq_cnt; qidx++) {
569+
cq = &qset->cq[qidx];
570+
if (cq->cq_type == CQ_RX)
571+
otx2_cleanup_rx_cqes(pf, cq);
572+
}
573+
565574
otx2_free_sq_res(pf);
566575

567576
/* Free RQ buffer pointers*/
@@ -901,6 +910,11 @@ static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id)
901910
*/
902911
pf->iommu_domain = iommu_get_domain_for_dev(dev);
903912

913+
netdev->hw_features = NETIF_F_RXCSUM;
914+
netdev->features |= netdev->hw_features;
915+
916+
netdev->hw_features |= NETIF_F_RXALL;
917+
904918
netdev->netdev_ops = &otx2_netdev_ops;
905919

906920
err = register_netdev(netdev);

‎drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h

Lines changed: 108 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,4 +28,112 @@ enum nix_send_ldtype {
2828
NIX_SEND_LDTYPE_LDWB = 0x2,
2929
};
3030

31+
/* NIX wqe/cqe types */
32+
enum nix_xqe_type {
33+
NIX_XQE_TYPE_INVALID = 0x0,
34+
NIX_XQE_TYPE_RX = 0x1,
35+
NIX_XQE_TYPE_RX_IPSECS = 0x2,
36+
NIX_XQE_TYPE_RX_IPSECH = 0x3,
37+
NIX_XQE_TYPE_RX_IPSECD = 0x4,
38+
NIX_XQE_TYPE_SEND = 0x8,
39+
};
40+
41+
/* NIX CQE/SQE subdescriptor types */
42+
enum nix_subdc {
43+
NIX_SUBDC_NOP = 0x0,
44+
NIX_SUBDC_EXT = 0x1,
45+
NIX_SUBDC_CRC = 0x2,
46+
NIX_SUBDC_IMM = 0x3,
47+
NIX_SUBDC_SG = 0x4,
48+
NIX_SUBDC_MEM = 0x5,
49+
NIX_SUBDC_JUMP = 0x6,
50+
NIX_SUBDC_WORK = 0x7,
51+
NIX_SUBDC_SOD = 0xf,
52+
};
53+
54+
/* NIX CQE header structure */
55+
struct nix_cqe_hdr_s {
56+
u64 flow_tag : 32;
57+
u64 q : 20;
58+
u64 reserved_52_57 : 6;
59+
u64 node : 2;
60+
u64 cqe_type : 4;
61+
};
62+
63+
/* NIX CQE RX parse structure */
64+
struct nix_rx_parse_s {
65+
u64 chan : 12;
66+
u64 desc_sizem1 : 5;
67+
u64 rsvd_17 : 1;
68+
u64 express : 1;
69+
u64 wqwd : 1;
70+
u64 errlev : 4;
71+
u64 errcode : 8;
72+
u64 latype : 4;
73+
u64 lbtype : 4;
74+
u64 lctype : 4;
75+
u64 ldtype : 4;
76+
u64 letype : 4;
77+
u64 lftype : 4;
78+
u64 lgtype : 4;
79+
u64 lhtype : 4;
80+
u64 pkt_lenm1 : 16; /* W1 */
81+
u64 l2m : 1;
82+
u64 l2b : 1;
83+
u64 l3m : 1;
84+
u64 l3b : 1;
85+
u64 vtag0_valid : 1;
86+
u64 vtag0_gone : 1;
87+
u64 vtag1_valid : 1;
88+
u64 vtag1_gone : 1;
89+
u64 pkind : 6;
90+
u64 rsvd_95_94 : 2;
91+
u64 vtag0_tci : 16;
92+
u64 vtag1_tci : 16;
93+
u64 laflags : 8; /* W2 */
94+
u64 lbflags : 8;
95+
u64 lcflags : 8;
96+
u64 ldflags : 8;
97+
u64 leflags : 8;
98+
u64 lfflags : 8;
99+
u64 lgflags : 8;
100+
u64 lhflags : 8;
101+
u64 eoh_ptr : 8; /* W3 */
102+
u64 wqe_aura : 20;
103+
u64 pb_aura : 20;
104+
u64 match_id : 16;
105+
u64 laptr : 8; /* W4 */
106+
u64 lbptr : 8;
107+
u64 lcptr : 8;
108+
u64 ldptr : 8;
109+
u64 leptr : 8;
110+
u64 lfptr : 8;
111+
u64 lgptr : 8;
112+
u64 lhptr : 8;
113+
u64 vtag0_ptr : 8; /* W5 */
114+
u64 vtag1_ptr : 8;
115+
u64 flow_key_alg : 5;
116+
u64 rsvd_383_341 : 43;
117+
u64 rsvd_447_384; /* W6 */
118+
};
119+
120+
/* NIX CQE RX scatter/gather subdescriptor structure */
121+
struct nix_rx_sg_s {
122+
u64 seg_size : 16; /* W0 */
123+
u64 seg2_size : 16;
124+
u64 seg3_size : 16;
125+
u64 segs : 2;
126+
u64 rsvd_59_50 : 10;
127+
u64 subdc : 4;
128+
u64 seg_addr;
129+
u64 seg2_addr;
130+
u64 seg3_addr;
131+
};
132+
133+
struct nix_cqe_rx_s {
134+
struct nix_cqe_hdr_s hdr;
135+
struct nix_rx_parse_s parse;
136+
struct nix_rx_sg_s sg;
137+
};
138+
31139
#endif /* OTX2_STRUCT_H */

0 commit comments

Comments
 (0)