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Will McVickerSylwester Nawrocki
Will McVicker
authored and
Sylwester Nawrocki
committed
clk: samsung: Update CPU clk registration
Convert the remaining exynos clock drivers to use samsung_clk_register_cpu() or if possible use samsung_cmu_register_one(). With this we can now make exynos_register_cpu_clock() a static function so that future CPU clock registration changes will use the samsung common clock driver. The main benefit of this change is that it standardizes the CPU clock registration for the samsung clock drivers. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Will McVicker <[email protected]> Tested-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> [[email protected]: Fixed build break in clk-exynos4.c, clk-exynos5250.c] Reported-by: kernel test robot <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
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6 files changed

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-57
lines changed

6 files changed

+67
-57
lines changed

‎drivers/clk/samsung/clk-cpu.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -400,7 +400,7 @@ static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb,
400400
}
401401

402402
/* helper function to register a CPU clock */
403-
int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
403+
static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
404404
unsigned int lookup_id, const char *name,
405405
const struct clk_hw *parent, const struct clk_hw *alt_parent,
406406
unsigned long offset, const struct exynos_cpuclk_cfg_data *cfg,

‎drivers/clk/samsung/clk-cpu.h

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -62,11 +62,4 @@ struct exynos_cpuclk {
6262
#define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2)
6363
};
6464

65-
int exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
66-
unsigned int lookup_id, const char *name,
67-
const struct clk_hw *parent, const struct clk_hw *alt_parent,
68-
unsigned long offset,
69-
const struct exynos_cpuclk_cfg_data *cfg,
70-
unsigned long num_cfgs, unsigned long flags);
71-
7265
#endif /* __SAMSUNG_CLK_CPU_H */

‎drivers/clk/samsung/clk-exynos3250.c

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -748,6 +748,31 @@ static const struct samsung_pll_clock exynos3250_plls[] __initconst = {
748748
UPLL_LOCK, UPLL_CON0, exynos3250_pll_rates),
749749
};
750750

751+
#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \
752+
(((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
753+
((corem) << 4))
754+
#define E3250_CPU_DIV1(hpm, copy) \
755+
(((hpm) << 4) | ((copy) << 0))
756+
757+
static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
758+
{ 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), },
759+
{ 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
760+
{ 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
761+
{ 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
762+
{ 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
763+
{ 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
764+
{ 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
765+
{ 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), },
766+
{ 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), },
767+
{ 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), },
768+
{ 0 },
769+
};
770+
771+
static const struct samsung_cpu_clock exynos3250_cpu_clks[] __initconst = {
772+
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
773+
CLK_CPU_HAS_DIV1, 0x14200, e3250_armclk_d),
774+
};
775+
751776
static void __init exynos3_core_down_clock(void __iomem *reg_base)
752777
{
753778
unsigned int tmp;
@@ -780,46 +805,21 @@ static const struct samsung_cmu_info cmu_info __initconst = {
780805
.nr_gate_clks = ARRAY_SIZE(gate_clks),
781806
.fixed_factor_clks = fixed_factor_clks,
782807
.nr_fixed_factor_clks = ARRAY_SIZE(fixed_factor_clks),
808+
.cpu_clks = exynos3250_cpu_clks,
809+
.nr_cpu_clks = ARRAY_SIZE(exynos3250_cpu_clks),
783810
.nr_clk_ids = CLK_NR_CLKS,
784811
.clk_regs = exynos3250_cmu_clk_regs,
785812
.nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),
786813
};
787814

788-
#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \
789-
(((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
790-
((corem) << 4))
791-
#define E3250_CPU_DIV1(hpm, copy) \
792-
(((hpm) << 4) | ((copy) << 0))
793-
794-
static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
795-
{ 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), },
796-
{ 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
797-
{ 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
798-
{ 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
799-
{ 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
800-
{ 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
801-
{ 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
802-
{ 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), },
803-
{ 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), },
804-
{ 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), },
805-
{ 0 },
806-
};
807-
808815
static void __init exynos3250_cmu_init(struct device_node *np)
809816
{
810817
struct samsung_clk_provider *ctx;
811-
struct clk_hw **hws;
812818

813819
ctx = samsung_cmu_register_one(np, &cmu_info);
814820
if (!ctx)
815821
return;
816822

817-
hws = ctx->clk_data.hws;
818-
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
819-
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C],
820-
0x14200, e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),
821-
CLK_CPU_HAS_DIV1);
822-
823823
exynos3_core_down_clock(ctx->reg_base);
824824
}
825825
CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);

‎drivers/clk/samsung/clk-exynos4.c

Lines changed: 14 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1228,6 +1228,16 @@ static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {
12281228
{ 0 },
12291229
};
12301230

1231+
static const struct samsung_cpu_clock exynos4210_cpu_clks[] __initconst = {
1232+
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_SCLK_MPLL,
1233+
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4210_armclk_d),
1234+
};
1235+
1236+
static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = {
1237+
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
1238+
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4412_armclk_d),
1239+
};
1240+
12311241
/* register exynos4 clocks */
12321242
static void __init exynos4_clk_init(struct device_node *np,
12331243
enum exynos4_soc soc)
@@ -1304,10 +1314,8 @@ static void __init exynos4_clk_init(struct device_node *np,
13041314
samsung_clk_register_fixed_factor(ctx,
13051315
exynos4210_fixed_factor_clks,
13061316
ARRAY_SIZE(exynos4210_fixed_factor_clks));
1307-
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1308-
hws[CLK_MOUT_APLL], hws[CLK_SCLK_MPLL], 0x14200,
1309-
e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
1310-
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
1317+
samsung_clk_register_cpu(ctx, exynos4210_cpu_clks,
1318+
ARRAY_SIZE(exynos4210_cpu_clks));
13111319
} else {
13121320
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
13131321
ARRAY_SIZE(exynos4x12_mux_clks));
@@ -1318,11 +1326,8 @@ static void __init exynos4_clk_init(struct device_node *np,
13181326
samsung_clk_register_fixed_factor(ctx,
13191327
exynos4x12_fixed_factor_clks,
13201328
ARRAY_SIZE(exynos4x12_fixed_factor_clks));
1321-
1322-
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1323-
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C], 0x14200,
1324-
e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
1325-
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
1329+
samsung_clk_register_cpu(ctx, exynos4412_cpu_clks,
1330+
ARRAY_SIZE(exynos4412_cpu_clks));
13261331
}
13271332

13281333
if (soc == EXYNOS4X12)

‎drivers/clk/samsung/clk-exynos5250.c

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -772,6 +772,11 @@ static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {
772772
{ 0 },
773773
};
774774

775+
static const struct samsung_cpu_clock exynos5250_cpu_clks[] __initconst = {
776+
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL, CLK_CPU_HAS_DIV1, 0x200,
777+
exynos5250_armclk_d),
778+
};
779+
775780
static const struct of_device_id ext_clk_match[] __initconst = {
776781
{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
777782
{ },
@@ -822,10 +827,8 @@ static void __init exynos5250_clk_init(struct device_node *np)
822827
ARRAY_SIZE(exynos5250_div_clks));
823828
samsung_clk_register_gate(ctx, exynos5250_gate_clks,
824829
ARRAY_SIZE(exynos5250_gate_clks));
825-
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
826-
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL], 0x200,
827-
exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
828-
CLK_CPU_HAS_DIV1);
830+
samsung_clk_register_cpu(ctx, exynos5250_cpu_clks,
831+
ARRAY_SIZE(exynos5250_cpu_clks));
829832

830833
/*
831834
* Enable arm clock down (in idle) and set arm divider

‎drivers/clk/samsung/clk-exynos5420.c

Lines changed: 18 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1551,6 +1551,20 @@ static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
15511551
{ 0 },
15521552
};
15531553

1554+
static const struct samsung_cpu_clock exynos5420_cpu_clks[] __initconst = {
1555+
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 0x200,
1556+
exynos5420_eglclk_d),
1557+
CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 0x28200,
1558+
exynos5420_kfcclk_d),
1559+
};
1560+
1561+
static const struct samsung_cpu_clock exynos5800_cpu_clks[] __initconst = {
1562+
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 0x200,
1563+
exynos5800_eglclk_d),
1564+
CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 0x28200,
1565+
exynos5420_kfcclk_d),
1566+
};
1567+
15541568
static const struct of_device_id ext_clk_match[] __initconst = {
15551569
{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
15561570
{ },
@@ -1625,17 +1639,12 @@ static void __init exynos5x_clk_init(struct device_node *np,
16251639
}
16261640

16271641
if (soc == EXYNOS5420) {
1628-
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1629-
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MSPLL_CPU], 0x200,
1630-
exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
1642+
samsung_clk_register_cpu(ctx, exynos5420_cpu_clks,
1643+
ARRAY_SIZE(exynos5420_cpu_clks));
16311644
} else {
1632-
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1633-
hws[CLK_MOUT_APLL], hws[CLK_MOUT_MSPLL_CPU], 0x200,
1634-
exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
1645+
samsung_clk_register_cpu(ctx, exynos5800_cpu_clks,
1646+
ARRAY_SIZE(exynos5800_cpu_clks));
16351647
}
1636-
exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
1637-
hws[CLK_MOUT_KPLL], hws[CLK_MOUT_MSPLL_KFC], 0x28200,
1638-
exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
16391648

16401649
samsung_clk_extended_sleep_init(reg_base,
16411650
exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs),

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