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Merge tag 'renesas-drivers-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers
Renesas driver updates for v5.8 - Add System Controller (SYSC) and Reset (RST) support for the new RZ/G1H (R8A7742) SoC. * tag 'renesas-drivers-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: rcar-rst: Add support for RZ/G1H soc: renesas: rcar-sysc: Add R8A7742 support clk: renesas: Add r8a7742 CPG Core Clock Definitions dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
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‎drivers/soc/renesas/Kconfig

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@@ -261,6 +261,10 @@ config ARCH_R8A77995
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endif # ARM64
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# SoC
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config SYSC_R8A7742
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bool "RZ/G1H System Controller support" if COMPILE_TEST
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select SYSC_RCAR
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config SYSC_R8A7743
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bool "RZ/G1M System Controller support" if COMPILE_TEST
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select SYSC_RCAR

‎drivers/soc/renesas/Makefile

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@@ -3,6 +3,7 @@
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obj-$(CONFIG_SOC_RENESAS) += renesas-soc.o
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# SoC
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obj-$(CONFIG_SYSC_R8A7742) += r8a7742-sysc.o
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obj-$(CONFIG_SYSC_R8A7743) += r8a7743-sysc.o
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obj-$(CONFIG_SYSC_R8A7745) += r8a7745-sysc.o
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obj-$(CONFIG_SYSC_R8A77470) += r8a77470-sysc.o

‎drivers/soc/renesas/r8a7742-sysc.c

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/G1H System Controller
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*/
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#include <linux/kernel.h>
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#include <dt-bindings/power/r8a7742-sysc.h>
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#include "rcar-sysc.h"
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static const struct rcar_sysc_area r8a7742_areas[] __initconst = {
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{ "always-on", 0, 0, R8A7742_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
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{ "ca15-scu", 0x180, 0, R8A7742_PD_CA15_SCU, R8A7742_PD_ALWAYS_ON,
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PD_SCU },
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{ "ca15-cpu0", 0x40, 0, R8A7742_PD_CA15_CPU0, R8A7742_PD_CA15_SCU,
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PD_CPU_NOCR },
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{ "ca15-cpu1", 0x40, 1, R8A7742_PD_CA15_CPU1, R8A7742_PD_CA15_SCU,
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PD_CPU_NOCR },
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{ "ca15-cpu2", 0x40, 2, R8A7742_PD_CA15_CPU2, R8A7742_PD_CA15_SCU,
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PD_CPU_NOCR },
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{ "ca15-cpu3", 0x40, 3, R8A7742_PD_CA15_CPU3, R8A7742_PD_CA15_SCU,
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PD_CPU_NOCR },
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{ "ca7-scu", 0x100, 0, R8A7742_PD_CA7_SCU, R8A7742_PD_ALWAYS_ON,
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PD_SCU },
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{ "ca7-cpu0", 0x1c0, 0, R8A7742_PD_CA7_CPU0, R8A7742_PD_CA7_SCU,
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PD_CPU_NOCR },
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{ "ca7-cpu1", 0x1c0, 1, R8A7742_PD_CA7_CPU1, R8A7742_PD_CA7_SCU,
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PD_CPU_NOCR },
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{ "ca7-cpu2", 0x1c0, 2, R8A7742_PD_CA7_CPU2, R8A7742_PD_CA7_SCU,
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PD_CPU_NOCR },
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{ "ca7-cpu3", 0x1c0, 3, R8A7742_PD_CA7_CPU3, R8A7742_PD_CA7_SCU,
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PD_CPU_NOCR },
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{ "rgx", 0xc0, 0, R8A7742_PD_RGX, R8A7742_PD_ALWAYS_ON },
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};
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const struct rcar_sysc_info r8a7742_sysc_info __initconst = {
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.areas = r8a7742_areas,
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.num_areas = ARRAY_SIZE(r8a7742_areas),
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};

‎drivers/soc/renesas/rcar-rst.c

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@@ -39,6 +39,7 @@ static const struct rst_config rcar_rst_gen3 __initconst = {
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static const struct of_device_id rcar_rst_matches[] __initconst = {
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/* RZ/G1 is handled like R-Car Gen2 */
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{ .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },
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{ .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
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{ .compatible = "renesas,r8a7744-rst", .data = &rcar_rst_gen2 },
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{ .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },

‎drivers/soc/renesas/rcar-sysc.c

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@@ -273,6 +273,9 @@ static int __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
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}
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static const struct of_device_id rcar_sysc_matches[] __initconst = {
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#ifdef CONFIG_SYSC_R8A7742
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{ .compatible = "renesas,r8a7742-sysc", .data = &r8a7742_sysc_info },
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#endif
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#ifdef CONFIG_SYSC_R8A7743
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{ .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },
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/* RZ/G1N is identical to RZ/G2M w.r.t. power domains. */

‎drivers/soc/renesas/rcar-sysc.h

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@@ -49,6 +49,7 @@ struct rcar_sysc_info {
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u32 extmask_val; /* SYSCEXTMASK register mask value */
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};
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extern const struct rcar_sysc_info r8a7742_sysc_info;
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extern const struct rcar_sysc_info r8a7743_sysc_info;
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extern const struct rcar_sysc_info r8a7745_sysc_info;
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extern const struct rcar_sysc_info r8a77470_sysc_info;

‎include/dt-bindings/clock/r8a7742-cpg-mssr.h

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/* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a7742 CPG Core Clocks */
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#define R8A7742_CLK_Z 0
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#define R8A7742_CLK_Z2 1
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#define R8A7742_CLK_ZG 2
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#define R8A7742_CLK_ZTR 3
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#define R8A7742_CLK_ZTRD2 4
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#define R8A7742_CLK_ZT 5
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#define R8A7742_CLK_ZX 6
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#define R8A7742_CLK_ZS 7
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#define R8A7742_CLK_HP 8
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#define R8A7742_CLK_B 9
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#define R8A7742_CLK_LB 10
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#define R8A7742_CLK_P 11
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#define R8A7742_CLK_CL 12
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#define R8A7742_CLK_M2 13
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#define R8A7742_CLK_ZB3 14
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#define R8A7742_CLK_ZB3D2 15
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#define R8A7742_CLK_DDR 16
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#define R8A7742_CLK_SDH 17
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#define R8A7742_CLK_SD0 18
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#define R8A7742_CLK_SD1 19
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#define R8A7742_CLK_SD2 20
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#define R8A7742_CLK_SD3 21
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#define R8A7742_CLK_MMC0 22
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#define R8A7742_CLK_MMC1 23
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#define R8A7742_CLK_MP 24
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#define R8A7742_CLK_QSPI 25
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#define R8A7742_CLK_CP 26
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#define R8A7742_CLK_RCAN 27
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#define R8A7742_CLK_R 28
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#define R8A7742_CLK_OSC 29
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#endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */

‎include/dt-bindings/power/r8a7742-sysc.h

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/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_POWER_R8A7742_SYSC_H__
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#define __DT_BINDINGS_POWER_R8A7742_SYSC_H__
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/*
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* These power domain indices match the numbers of the interrupt bits
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* representing the power areas in the various Interrupt Registers
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* (e.g. SYSCISR, Interrupt Status Register)
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*/
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#define R8A7742_PD_CA15_CPU0 0
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#define R8A7742_PD_CA15_CPU1 1
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#define R8A7742_PD_CA15_CPU2 2
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#define R8A7742_PD_CA15_CPU3 3
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#define R8A7742_PD_CA7_CPU0 5
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#define R8A7742_PD_CA7_CPU1 6
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#define R8A7742_PD_CA7_CPU2 7
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#define R8A7742_PD_CA7_CPU3 8
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#define R8A7742_PD_CA15_SCU 12
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#define R8A7742_PD_RGX 20
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#define R8A7742_PD_CA7_SCU 21
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/* Always-on power area */
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#define R8A7742_PD_ALWAYS_ON 32
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#endif /* __DT_BINDINGS_POWER_R8A7742_SYSC_H__ */

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